Technical Product Specification

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Intel® Server Board S5500BC

Intel order number: E42249-009

Revision 1.8

June 2011

Enterprise Platforms and Services Division – Marketing

Summary of content (162 pages)

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Intel®Server Board S5500BC Technical Product Specification Intel order number: E42249-009 Revision 1.
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Revision History Intel®Server Board S5500BC TPS Revision History Date Revision Number Modifications January 2009 1.0 Initial Release. February, 2009 1.1  Replaced RRL MIC Mark with RRL KCC Mark  Removed lock step description from BIOS RAS  Updated Table ―POST Error Beep Codes‖ according to BIOS EPS  Added Chapter 5 – BIOS screen shots  Updated Table ―Diagnostic LED POST Code Decoder‖  Updated section 3.2.1~3.2.
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Intel®Server Board S5500BC TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel®Server Board S5500BC TPS Table of Contents 1. Introduction .......................................................................................................................... 1 1.1 2. 3. Product Overview ................................................................................................................. 2 2.1 Feature Set .............................................................................................................. 2 2.
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Intel®Server Board S5500BC TPS 3.3.5 3.4 Intel® Virtualization Technology for Directed I/O (Intel® VT-d) (rev. 2) ................... 32 Intel® 82801Jx I/O Controller Hub (ICH10R).......................................................... 33 3.4.1 PCI and PCI Express* Interfaces ........................................................................... 33 3.4.2 Serial ATA II Interface ............................................................................................ 33 3.4.
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Table of Contents 4.2.4 Availability .............................................................................................................. 49 4.2.5 Web Services for Management (WS-MAN) ........................................................... 49 4.2.6 Lightweight Directory Authentication Protocol (LDAP) .......................................... 49 4.2.7 Embedded Web server .......................................................................................... 49 4.
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Intel®Server Board S5500BC TPS Table of Contents 6.8 SGPIO Header ....................................................................................................... 98 6.9 Chassis Intrusion Header ...................................................................................... 98 6.10 SMB Hot-Swap Backplane (HSBP) Header........................................................... 98 6.11 SATA RAID Key Header .................................................................................
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Table of Contents 10.1 Intel®Server Board S5500BC TPS Product Regulatory Compliance .......................................................................... 115 10.1.1 Product Safety Compliance ................................................................................. 115 10.1.2 Product EMC Compliance – Class A Compliance ............................................... 116 10.1.3 Certifications / Registrations / Declarations .........................................................
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Intel®Server Board S5500BC TPS List of Figures List of Figures Figure 1. Intel® Server Board S5500BC Picture............................................................................ 4 Figure 2. Intel® Server Board S5500BC Layout ............................................................................ 5 Figure 3. Key Connector and LED Indicator Identification ............................................................ 6 Figure 4. Mounting Hole Location ..............................................
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List of Figures Intel®Server Board S5500BC TPS Figure 32. Setup Utility — Server Management System Information Screen Display ................ 79 Figure 33. Setup Utility — Boot Options Screen Display ............................................................ 80 Figure 34. Setup Utility — Add New Boot Option Screen Display .............................................. 82 Figure 35. Setup Utility — Delete Boot Option Screen Display .................................................. 82 Figure 36.
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Intel®Server Board S5500BC TPS List of Tables List of Tables Table 1: Feature Description ......................................................................................................... 2 Table 2. Board Layout reference .................................................................................................. 5 Table 3. Intel® Light-Guided Diagnostic LED reference .............................................................. 13 Table 4. External I/O Layout Reference ....................
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List of Tables Intel®Server Board S5500BC TPS Table 31. Setup Utility — Add New Boot Option Fields .............................................................. 82 Table 32. Setup Utility — Delete Boot Option Fields .................................................................. 83 Table 33. Setup Utility — Hard Disk Order Fields ....................................................................... 83 Table 34. Setup Utility — CDROM Order Fields ......................................................
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Intel®Server Board S5500BC TPS List of Tables Table 66. Power on loading range ............................................................................................ 107 Table 67. Voltage Regulation Limits ......................................................................................... 109 Table 68. Transient Load Requirements ................................................................................... 109 Table 69. Capacitive Loading Conditions ......................................
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List of Tables Intel®Server Board S5500BC TPS < This page intentionally left blank. > xiv Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Introduction 1. Introduction This Technical Product Specification (TPS) provides board-specific information about the features, functionality, and high-level architecture of the Intel® Server Board S5500BC. The Intel® Server Board S5500BC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Refer to the Intel® Server Board S5500BC Specification Update for published errata. 1.
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Product Overview Intel®Server Board S5500BC TPS 2. Product Overview The Intel® Server Board S5500BC are monolithic printed circuit board (PCB) that supports the high-density 1U rack-mount server and 5U pedestal server market. 2.1 Feature Set Table 1: Feature Description Feature Description Processors LGA 1366 sockets supporting up to two Intel® Xeon® processor 5500 series and 5600 series with Intel® QuickPath Interconnect (QPI) and Integrated Memory controllers.
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Intel®Server Board S5500BC TPS Feature Add-in PCI, PCI Express* Cards      Onboard Video LAN     USB Power Supply System Management Revision 1.8 Slot4: 5-V PCI 32 bit / 33 MHz connector that supports half-length (6.6 inches) adapter 64 MB DDR2 667 MHz memory Support up to six Serial ATA II hard drives through six onboard SATA II connectors  Fans Description Slot6: PCI Express* Gen2 x8 connector with X8 link width that supports half-length (6.
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Product Overview Intel®Server Board S5500BC TPS 2.2 Server Board Layout Figure 1. Intel® Server Board S5500BC Picture 2.2.1 Server Board Connector and Component Layout Figure 2 shows the board layout of the server board. Each connector and major component is identified by a number or letter, and a description is below the figure. 4 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Product Overview Figure 2. Intel® Server Board S5500BC Layout Table 2. Board Layout reference A SATA 3 Description B Description Internal dual port USB2.
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Product Overview Intel®Server Board S5500BC TPS Description Description AA CPU Socket 2 BB CPU 2 fan header CC System fan 1 header DD DIMM sockets for Channels D and E (Supports CPU_2) EE SATA SGPIO FF SATA 0 GG SATA 1 HH SATA 2 2.2.2 Server Board Mechanical Drawing Figure 3. Key Connector and LED Indicator Identification 6 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Product Overview Figure 4. Mounting Hole Location Revision 1.
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Product Overview Intel®Server Board S5500BC TPS Figure 5. Major Connector Pin-1 Locations 8 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Product Overview Figure 6. Intel® Server Board S5500BC Board Primary Side Keepouts Revision 1.
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Product Overview Intel®Server Board S5500BC TPS Figure 7. Intel® Server Board S5500BC Board Primary Side Card-Side Keepout Zone 10 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Product Overview Figure 8. Secondary Side Keepout -- Mounting Hole Keepout Revision 1.
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Product Overview Intel®Server Board S5500BC TPS Figure 9. Secondary Side Keepout - CPU Socket and Rubber Pad Keepout 12 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Product Overview 2.2.3 Intel® Light-Guided Diagnostic LED Locations Figure 10. Intel® Light-Guided Diagnostic LED Locations Table 3. Intel® Light-Guided Diagnostic LED reference Revision 1.
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Product Overview Intel®Server Board S5500BC TPS 2.2.4 External I/O Connector Locations Figure 11. External I/O Layout Table 4. External I/O Layout Reference 14 A Description Serial Port A B Video Description C USB Port 6-7 D USB Port 8-9 E NIC Port 1 F NIC Port 2 (management port) Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Functional Architecture 3. Functional Architecture The architecture and design of the Intel® Server Board S5500BC is based on the Intel® 5500 chipset and the Intel® Xeon® processor 5500 series and 5600 series. This chapter provides a high-level description of the functionality associated with each chipset component and architectural blocks that make up this server board. Figure 12. Functional Block Diagram 3.
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Functional Architecture Intel®Server Board S5500BC TPS Table 5. Intel® Xeon® Processor 5500 Series Feature Set Overview Feature Intel®Xeon®Processor 5500 Series and 5600 Series Cache Sizes Instruction Cache = 32 KB Data Cache = 32 KB 8 MB shared among cores (up to 4) Data Transfer Rate Two full-width Intel® QuickPath Interconnect links, up to 6.4 GT/s in each direction. Multi-Core Support Up to four cores per processor. Dual Processor Support Up to two processors per platform.
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Intel®Server Board S5500BC TPS Functional Architecture Intel® Xeon® 5500 processor Intel® Xeon® 5500 processor Core– 0 …. Core– 3 Core– 0 Cache Mem I/F …. Core– 3 Cache CSI Interface CSI Interface Mem I/F Memory Memory Intel® 5500 I/O Hub CSI Link CSI Interface PCI-E PCI-E PCI-E Figure 13. Intel® IOH 5500 Chipset with Intel® QuickPath Interconnect Block Diagram 3.1.
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Functional Architecture Intel®Server Board S5500BC TPS The following table describes mixed processor conditions and recommended actions for all Intel® server boards and systems that use the Intel® IOH chipset. Errors fall into one of two categories:  Fatal: If the system can boot, it goes directly to the error manager, regardless of the ―Post Error Pause‖ set-up option.
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Intel®Server Board S5500BC TPS Error Processor microcode missing Functional Architecture Severity Fatal System Action The BIOS detects the error condition and responds as follows: 1. Logs the error into the SEL. 2. Alerts the BMC of the configuration error with an IPMI command. 3. Does not disable the processor. 4. Displays “816x: Processor 0x unable to apply microcode update” message in the error manager. 5. Pauses the system for user intervention.
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Functional Architecture Intel®Server Board S5500BC TPS 3.1.4 Turbo Mode The Turbo Mode feature opportunistically and automatically allows the CPU to run faster than the TDP frequency if the processor is operating below specifications. The processor must be below the power, temperature, and current specification limits. Turbo Mode increases performance of both multi-threaded and single-threaded workloads.
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Intel®Server Board S5500BC TPS Functional Architecture 3.1.8 Independent Loading Mechanism (ILM) Back Plate Design Support The Intel® Server board S5500BC complies with Intel‘s Independent Loading Mechanism (ILM) processor mounting and Unified Retention System (URS) heatsink retention solution. The ILM design allows a bottoms-up assembly of the components to the board.
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Functional Architecture Intel®Server Board S5500BC TPS Figure 14. ILM Backplate and URS 3.2 Memory Subsystem 3.2.1 Supported Memory The Intel® Xeon® processors 5500 series and 5600 series have an Integrated Memory Controller (IMC). The Intel® Server Board S5500BC memory interface supports two DDR3 channels. Each channel consists of 64 data and 8 ECC bits. The IMC provides DDR3 channels 22 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Functional Architecture and groups DIMMs on the board into an autonomous RAS memory. The server board is designed to support a DDR3-based memory subsystem with eight DIMM slots.
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Functional Architecture Intel®Server Board S5500BC TPS The rules for determining the operating frequency of the memory channels are simple, but not necessarily straightforward. There are several limiting factors, including the number of DIMMs on a channel and organization of the DIMM (single-SR, double-DR, or quad-rank-QR):  The speed of the processor‘s IMC – 800, 1066, or 1333 MHz – is the maximum speed possible.
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Intel®Server Board S5500BC TPS Functional Architecture Table 9. Memory Operating Frequency Determination for Intel® processor 5600 series and 1.
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Functional Architecture Intel®Server Board S5500BC TPS 3.2.2 DIMM Population Requirements DIMMs on this board are organized into physical slots on the DDR3 memory channels divided between two processor sockets. For more information, refer to the following figure. Processor Socket 1 Channel A A1 Processor Socket 2 Channel B A2 B1 B2 Channel D D1 D2 Channel E E1 E2 Figure 15.
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Intel®Server Board S5500BC TPS  Functional Architecture Sockets are self-contained and autonomous. However, all RAS Error Management configurations in the BIOS setup are applied commonly across sockets. Figure 16. Channel slots Configuration 3.2.3 Memory Upgrade Guidelines Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the following factors:  The current RAS mode of operation.  The existing DDR3 DIMM population.  The DDR3 DIMM characteristics.
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Functional Architecture Intel®Server Board S5500BC TPS  The Independent Channel Mode is the default maximum performance mode preferred for Intel® Xeon® processor 5500 series and 5600 series based platforms.  Socket1 usually has precedence over socket 2 in determining the possible RAS modes.  The sockets are autonomous and capable of being independently initialized. However, the minimal upgrade for socket 2 is DIMM_D1 in Independent Channel Mode.
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Intel®Server Board S5500BC TPS Functional Architecture The Intel® Xeon® processor 5500 series and 5600 series on sockets 1 and 2 in a dual-processor configuration are completely autonomous. DIMMs routed to sockets are isolated and can be initialized locally, including RAS configurations. The Intel® Server Board S5500BC provide one set of RAS questions in the BIOS Setup and can configure common RAS features across the sockets.
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Functional Architecture Intel®Server Board S5500BC TPS  Two x16 PCI Express* Gen2 ports are also configurable as x8 and x4 links compliant to the PCI Express* Base Specification, Revision 2.0. Each port supports up to 8 GB/s/direction peak bandwidth.  One x4 Enterprise South Bridge Interface (ESI) link interface.  Support Controller Link interface between the IOH and ICH portions of the Manageability Engine subsystem.
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Intel®Server Board S5500BC TPS Functional Architecture Server Platform Services are value-added platform management options that enhance the value of Intel platforms and their component ingredients (CPUs, chipsets and I/O components). Each service is designed to function independently wherever possible, or grouped together with one or more features in flexible combinations to allow OEMs (Original Equipment Manufacturers) to differentiate platforms.
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Functional Architecture Intel®Server Board S5500BC TPS  BMC initializes ME-owned sensors based on SDRs.  BMC receives platform event messages sent by the ME.  BMC notifies ME of POST completion.  BMC may be queried by the ME for inlet temperature readings. 3.3.5 Intel® Virtualization Technology for Directed I/O (Intel ® VT-d) (rev.
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Intel®Server Board S5500BC TPS Functional Architecture 3.4 Intel® 82801Jx I/O Controller Hub (ICH10R) The Intel® ICH10R I/O Controller Hub provides extensive I/O support. Functions and capabilities include:  PCI Express* Base Specification, Revision 1.1 support  PCI Local Bus Specification, Revision 2.3 for 33 MHz PCI operations (supports up to four REQ#/GNT# pairs)  ACPI Power Management Logic Support, Revision 3.
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Functional Architecture Intel®Server Board S5500BC TPS The BIOS Setup utility provides multiple drive configuration options on the Advanced | Mass Storage Controller Configuration setup page, some of which affect the ability to configure RAID. The ―Onboard SATA Controller‖ option is enabled by default. When this option is enabled, you can set the ―SATA Mode‖ option to ENHANCED mode, COMPATIBILITY mode, AHCI mode, or SW RAID mode.
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Intel®Server Board S5500BC TPS Functional Architecture six Universal Host Controller Interface (UHCI) controllers that support USB full-speed and lowspeed signaling. The Intel® ICH10R supports up to 12 USB 2.0 ports. All 12 ports are high-speed, full-speed, and low-speed capable. Intel® ICH10R‘s port-routing logic determines whether a USB port is controlled by one of the UHCI or EHCI controllers.
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Functional Architecture   Intel®Server Board S5500BC TPS Keeps track of the time of day Stores System configuration data even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3-V lithium battery. 3.4.11 Manageability Intel® ICH10R integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system.
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Intel®Server Board S5500BC TPS Functional Architecture 82567 Gigabit Network connector drive two LEDs located on each network interface connector (NIC). The normal RJ45 link/activity LED at the right of the connector indicates network connection when on and Transmit/Receive activity when blinking. These LEDs are be powered from a Standby voltage rail. The speed LED at the left indicates 1000 Mbps operation when amber; 100 Mbps operation when green; and 10 Mbps when off. Table 12.
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Functional Architecture Intel®Server Board S5500BC TPS  IPMI MC pass-through; multi-drop NC-SI  TimeSync offload compliant with 802.1AS specification 3.5.2 Intel® 82567 Gigabit Network Connection Physical Layer Transceiver (PHY) The Intel® 82567 Gigabit Network Transceiver is a single-port Gigabit Network Layer Transceiver (PHY) that connects to the Media Access Controller (MAC) through a dedicated interconnect.
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Intel®Server Board S5500BC TPS Functional Architecture  SMI/SCI/PME Support  ACPI Compliant  Up to 16 shared GPIO ports  Programmable Wake-up Event Support  Plug and Play Register Set  Power Supply Control  Watchdog timer compliant with Microsoft SHDG*  LPC to SPI bridge for system BIOS support  Real Time Clock (RTC) module with the external RTC interface Baseboard Management Controller Features:  IPMI 2.
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Functional Architecture Intel®Server Board S5500BC TPS Remote KVMS Features:  USB 2.0 interface for Keyboard, Mouse, and Remote storage, such as a CD/DVD-ROM and floppy  USB 1.
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Intel®Server Board S5500BC TPS Functional Architecture Integrated BMC Block Diagram Interrupt Controller Fan Tach (12) PWM (4) ADC Thermal USB to Host Code Memory USB 1.1 & USB 2.
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Functional Architecture  Intel®Server Board S5500BC TPS All users disabled For more information about BMC IP address configuration, refer to the Intel® S5500 Chipset Server Board Baseboard Management Controller Core External Product Specification. 3.7 Video Support The Intel® Server Board S5500BC includes a video controller in the onboard ServerEngines* LLC Pilot II BMC and 8 MB of video DDR2 SDRAM. The SVGA subsystem supports a variety of modes—up to 1600 x 1000 resolution in 8/16/32 bpp under 2D.
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Intel®Server Board S5500BC TPS Functional Architecture 3.10 Keyboard and Mouse Support The server board does not support PS/2 interface keyboards and mice. However, the system BIOS recognizes USB specification-compliant keyboard and mice. 3.11 Wake-up Control The BMC allows events to power-on and power-off the system. Wake from S1 is supported on LAN, USB, Serial port, and PCI Express* slots. 3.
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Platform Management Intel®Server Board S5500BC TPS 4. Platform Management The Platform Management subsystem on the Intel® Server Board S5500BC consists of a Baseboard Management Controller (BMC), server management buses, sensors, server management firmware, and system BIOS. The BMC is provided by ServerEngines* Pilot II integrated Baseboard Management Controller (Integrated BMC).
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Intel®Server Board S5500BC TPS Platform Management Figure 18. SMBUS Block Diagram Revision 1.
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Platform Management Intel®Server Board S5500BC TPS 4.1 Feature Support 4.1.1 IPMI 2.0 Features  Baseboard management controller (BMC).  IPMI Watchdog timer.  Messaging support, including command bridging and user/session support.  Chassis device functionality, including power/reset control and BIOS boot flags support.  Event receiver device: The BMC receives and processes events from other platform subsystems.
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Intel®Server Board S5500BC TPS Platform Management  Power supply redundancy monitoring and support.  Hot-swap fan support.  Acoustic management: Support for multiple fan profiles.  Signal testing support: The BMC provides test commands for setting and getting platform signal states.  The BMC generates diagnostic beep codes for fault conditions.  System GUID storage and retrieval.  Front panel management: The BMC controls the system status LED and chassis ID LED.
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Platform Management Intel®Server Board S5500BC TPS 4.2.2 Keyboard, Video, Mouse (KVM) Redirection The BMC firmware supports keyboard, video, and mouse redirection over LAN. This feature is available remotely from the embedded web server as a Java applet. This feature is only enabled when the RMM3 is present.  Keyboard and Mouse The keyboard and mouse are emulated by the BMC as USB human interface devices.
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Intel®Server Board S5500BC TPS Platform Management  The mounted device is visible to (and useable by) the managed system‘s operating system and BIOS in both pre-boot and post-boot states.  The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device.  It is possible to install an operating system on an empty drive using the remotely mounted device.
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Platform Management Intel®Server Board S5500BC TPS 4.3 Console Redirection The BIOS supports redirection of both video and keyboard via a serial link (serial port). When console redirection is enabled, the local (host server) keyboard input and video output are passed both to the local keyboard and video connections, and to the remote console through the serial link. Keyboard inputs from both sources are considered valid and video displays to both outputs.
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Intel®Server Board S5500BC TPS Platform Management SOL Found Active: The BIOS prioritizes SOL over Serial B Console Redirection. The BIOS queries the BMC for SOL Baud Rate and overrides the setup Serial B Console Redirection Baud with SOL Baud Rate. The BIOS also enables Hardware Flow control between the BIOS and BMC and forces terminal emulation type as PC-ANSI. Since Serial B is a shared port between the BIOS and BMC, if SOL is found active, the user sees no data on Serial B port.
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Platform Management Intel®Server Board S5500BC TPS secondary IPMB. The BMC does not own any platform event filters or traps for NM-related events. You should configure these events in the NM by server management software. 4.4.3 External Communications Link The BMC bridges commands between external software agents and the system‘s ME using standard IPMI Send Message commands. See the command bridging section in the Intelligent Platform Management Interface Specification Second Generation v2.
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Intel®Server Board S5500BC TPS Platform Management At system startup, the ME may query the BMC for the following information using IPMI OEM commands: Inlet air temperature reading – This corresponds to the temperature reading from the Front Panel Ambient Temperature sensor. Some platforms may not support this feature. Refer to the applicable platform appendix. 4.4.6 ACPI Mode Notification The BIOS notifies the BMC when the system enters and exits ACPI mode. The BMC, in turn, notifies the ME.
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BIOS Setup Utility Intel®Server Board S5500BC TPS 5. BIOS Setup Utility 5.1 Logo / Diagnostic Screen The Logo / Diagnostic Screen appears in one of two forms:  If Quiet Boot is enabled in the BIOS setup, a logo splash screen is displayed. By default, Quiet Boot is enabled in the BIOS setup. If the logo is displayed during POST, press to hide the logo and display the diagnostic screen.
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Intel®Server Board S5500BC TPS BIOS Setup Utility  Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® server board BIOS is only available in English.  Console Redirection - The BIOS Setup is functional via console redirection over various terminal emulation standards.
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BIOS Setup Utility Intel®Server Board S5500BC TPS Table 15. BIOS Setup: Keyboard Command Bar Key Option Execute Command Description The key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date.
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Intel®Server Board S5500BC TPS BIOS Setup Utility 5.3.1.4 Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen. It displays the major menu selections available to the user. By using the left and right arrow keys, the user can select the menus listed here. Some menus are hidden and become available by scrolling off the left or right of the current selections. 5.3.
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BIOS Setup Utility  Main Advance d Intel®Server Board S5500BC TPS Security Server Management Boot Options Boot Manager   Logged in as   Platform ID  System BIOS  Version SXXXX.86B.xx.yy.zzzz Build Date    Memory  Total Memory   Quiet Boot Enabled/Disabled POST Error Pause Enabled/Disabled  System Date  System Time   Figure 19.
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Intel®Server Board S5500BC TPS Setup Item BIOS Setup Utility Options Help Text Size Quiet Boot POST Error Pause Comments Information only. Displays the total physical memory installed in the system, in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR-3 DIMMs. [Enabled] – Display the logo screen during POST. Enabled Disabled [Disabled] – Display the diagnostic screen during POST. [Enabled] – Go to the Error Manager for critical POST errors.
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BIOS Setup Utility Main Intel®Server Board S5500BC TPS Advance d Security Server Management Boot Options Boot Manager  ► Processor Configuration ► Memory Configuration ► Mass Storage Controller Configuration ► Serial Port Configuration ► USB Configuration ► PCI Configuration ► System Acoustic and Performance Configuration  Figure 20. Setup Utility — Advanced Screen Display Table 17.
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Intel®Server Board S5500BC TPS BIOS Setup Utility Advanced Processor Configuration Processor Socket Processor ID Processor Frequency Microcode Revision L1 Cache RAM L2 Cache RAM L3 Cache RAM CPU 1 Size of Cache Size of Cache Size of Cache CPU 2 Size of Cache Size of Cache Size of Cache Processor 1 Version Processor 2 Version or Not Present Current Intel® QPI Link Speed Intel® QPI Li
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BIOS Setup Utility Intel®Server Board S5500BC TPS Setup Item Microcode Revision Options Help Text Comments Information only. Revision of the loaded microcode. L1 Cache RAM Information only. Size of the Processor L1 Cache. L2 Cache RAM Information only. Size of the Processor L2 Cache L3 Cache RAM Information only. Size of the Processor L3 Cache. Processor 1 Version Information only. ID string from the Processor. Processor 2 Version Information only. ID string from the Processor.
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Intel®Server Board S5500BC TPS Setup Item Interrupt Remapping Options Enabled Disabled Coherency Support Enabled Disabled ATS Support Enabled Disabled Pass-through DMA Support Enabled Hardware Prefetcher Enabled Disabled Disabled BIOS Setup Utility Help Text Enable/Disable Intel® VT-d Interrupt Remapping support. Comments Only appears when Intel® Virtualization Technology for Directed I/O is enabled. Enable/Disable Intel® VT-d Coherency support.
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BIOS Setup Utility Intel®Server Board S5500BC TPS Advanced Memory Configuration Total Memory Effective Memory Current Configuration Current Memory Speed
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Intel®Server Board S5500BC TPS Setup Item Current Configuration Options BIOS Setup Utility Help Text Comments Information only. Displays one of the following: Independent Mode: System memory is configured for optimal performance and efficiency and no RAS is enabled. Mirror Mode: System memory is configured for maximum reliability in the form of memory mirroring. Sparing Mode: System memory is configured for RAS with optimal effective memory.
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BIOS Setup Utility Intel®Server Board S5500BC TPS Advanced Memory RAS and Performance Configuration Capabilities Memory Mirroring Possible Yes / No Memory Sparing Possible Select Memory RAS Configuration Yes / No Maximum Performance / Mirroring / Sparing NUMA Optimized Disabled/ Enabled Figure 23. Setup Utility — Configure RAS and Performance Screen Display Table 20.
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Intel®Server Board S5500BC TPS BIOS Setup Utility Advanced Mass Storage Controller Configuration Intel(R) Entry SAS RAID Module Configure Intel(R) Entry SAS RAID Module Onboard SATA Controller Enabled / Disabled Configure SATA Mode LSI® Integrated RAID / Intel® ESRTII Enabled / Disabled ENHANCED / COMPATIBILITY / AHCI / SW RAID ► SATA Port 0 Not Installed/ ► SATA Port 1 Not Installed/ ► SATA Port 2 Not Installed/ ► SATA Port 3 Not Installed/
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BIOS Setup Utility Setup Item SATA Mode Intel®Server Board S5500BC TPS Options ENHANCED COMPATIBILIT Y AHCI SW RAID Help Text [ENHANCED] - Supports up to 6 SATA ports with IDE Native Mode. [COMPATIBILITY] - Supports up to 4 SATA ports [0/1/2/3] with IDE Legacy mode and 2 SATA ports [4/5] with IDE Native Mode. [AHCI] - Supports all SATA ports using the Advanced Host Controller Interface. [SW RAID] - Supports configuration of SATA ports for RAID via RAID configuration software.
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Intel®Server Board S5500BC TPS BIOS Setup Utility Advanced Serial Port Configuration  Serial A Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4    Figure 25. Setup Utility — Serial Port Configuration Screen Display Table 22. Setup Utility — Serial Ports Configuration Screen Fields Setup Item Options Enabled Disabled Help Text Enable or Disable Serial port A.
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BIOS Setup Utility Intel®Server Board S5500BC TPS Advanced USB Configuration Detected USB Devices USB Controller Enabled / Disabled Legacy USB Support Enabled / Disabled / Auto Port 60/64 Emulation Enabled / Disabled Make USB Devices Non-Bootable Enabled / Disabled USB Mass Storage Device Configuration 10 seconds / 20 seconds / 30 seconds / 40 seconds Device Reset timeout Mass Storage Devices: Auto / Floppy/Forced FDD/Hard Dis
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Intel®Server Board S5500BC TPS Setup Item Make USB Devices NonBootable Options Enabled Device Reset timeout 10 sec One line for each mass storage device in system USB 2.0 controller BIOS Setup Utility Help Text Exclude USB in Boot Table. [Enabled] - This removes all USB Mass Storage devices as Boot options. [Disabled] - This allows all USB Mass Storage devices as Boot options. Comments Grayed out if the USB Controller is disabled. USB Mass Storage device Start Unit command timeout.
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BIOS Setup Utility   Intel®Server Board S5500BC TPS  Advanced PCI Configuration Maximize Memory below 4GB Enabled / Disabled Memory Mapped I/O above 4GB Enabled / Disabled Onboard Video Enabled / Disabled Dual Monitor Video Enabled / Disabled Onboard NIC1 ROM Enabled / Disabled Onboard NIC2 ROM Enabled / Disabled Onboard NIC iSCSI ROM Enabled / Disabled NIC 1 MAC Address NIC 2 MAC Address Figure 27. Setup Utility — PCI Configuration Screen Display Table 24.
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Intel®Server Board S5500BC TPS Setup Item NIC 1 MAC Address Options No entry allowed NIC 2 MAC Address No entry allowed BIOS Setup Utility Help Text Comments Information only. 12 hex digits of the MAC address. Information only. 12 hex digits of the MAC address. 5.3.2.2.7 System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal characteristics of the system.
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BIOS Setup Utility Setup Item Set Fan Profile Intel®Server Board S5500BC TPS Options Performance Acoustics Help Text [Performance] - Fan control provides primary system cooling before attempting to throttle memory. [Acoustic] - The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met. Comments This option is grayed out if CLTT is enabled. 5.3.2.
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Intel®Server Board S5500BC TPS Setup Item Set Administrator Password BIOS Setup Utility Options [123aBcD] Help Text Administrator password is used to control change access in BIOS Setup Utility. Only alphanumeric characters can be used. Maximum length is 7 characters. It is case sensitive. Note: Administrator password must be set in order to use the user account. Set User Password [123aBcD] User password is used to control entry access to BIOS Setup Utility. Only alphanumeric characters can be used.
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BIOS Setup Utility Intel®Server Board S5500BC TPS 5.3.2.4 Server Management Screen The Server Management screen allows the user to configure several server management features. This screen also provides an access point to the screens for configuring console redirection and displaying system information. To access this screen from the Main screen, select Server Management.
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Intel®Server Board S5500BC TPS BIOS Setup Utility Setup Item Clear System Event Log Options Enabled FRB-2 Enable Enabled Disabled Fault Resilient Boot (FRB). If enabled, the BIOS programs the BMC watchdog timer for approximately 6 minutes. If the BIOS does not complete POST before the timer expires, the BMC resets the system. O/S Boot Watchdog Timer Enabled If enabled, the BIOS programs the watchdog timer with the timeout value selected.
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BIOS Setup Utility Intel®Server Board S5500BC TPS  Server Management  Console Redirection Console Redirection Disabled / Serial Port A / Serial Port B Flow Control None / RTS/CTS Baud Rate 9.6k / 19.2k / 38.4k / 57.6k / 115.2k Terminal Type PC-ANSI / VT100 / VT100+ / VT-UTF8 Legacy OS Redirection Disabled / Enabled Figure 31. Setup Utility — Console Redirection Screen Display Table 28.
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Intel®Server Board S5500BC TPS BIOS Setup Utility To access this screen from the Main screen, select Server Management > System Information. Server Management   System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 32. Setup Utility — Server Management System Information Screen Display Table 29.
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BIOS Setup Utility  Main Intel®Server Board S5500BC TPS Advance d Security Server Management Boot Options System Boot Timeout <0 - 65535> Boot Option #1 Boot Option #2 Boot Option #x Boot Manager  Hard Disk Order CDROM Order Floppy Order Network Device Order BEV Device Order Add New Boot Option ►Delete Boot Option EFI Optimized Boot Enabled / Disabled Use Legacy Video for EFI OS Enabled / Disabled Boot Option
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Intel®Server Board S5500BC TPS Setup Item Boot Option #x BIOS Setup Utility Options Available boot devices. Help Text Set system boot order by selecting the boot option for this position. Comments Hard Disk Order Set the order of the legacy devices in this group. Appears when 1 or more hard disk drives are in the system. CDROM Order Set the order of the legacy devices in this group. Appears when 1 or more CD-ROM drives are in the system.
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BIOS Setup Utility Intel®Server Board S5500BC TPS 5.3.2.6.1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order. To access this screen from the Main screen, select Boot Options > Delete Boot Options.  Boot Options  Add New Boot Option Add boot option label Select File system Path for boot option Save Figure 34. Setup Utility — Add New Boot Option Screen Display Table 31.
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Intel®Server Board S5500BC TPS BIOS Setup Utility Table 32. Setup Utility — Delete Boot Option Fields Setup Item Delete Boot Option Options Select one to Delete Internal EFI Shell Help Text Remove an EFI boot option from the boot order. 5.3.2.6.3 Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks. To access this screen from the Main screen, select Boot Options > Hard Disk Order.
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BIOS Setup Utility Intel®Server Board S5500BC TPS Table 34. Setup Utility — CDROM Order Fields Setup Item CDROM #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. CDROM #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position. 5.3.2.6.5 Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives.
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Intel®Server Board S5500BC TPS BIOS Setup Utility Boot Options  Network Device #1 Network Device #2  Figure 39. Setup Utility — Network Device Order Screen Display Table 36. Setup Utility — Network Device Order Fields Setup Item Network Device #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position.
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BIOS Setup Utility Intel®Server Board S5500BC TPS 5.3.2.7 Boot Manager Screen The Boot Manager screen allows the user to view a list of devices available for booting, and to select a boot device for immediately booting the system. To access this screen from the Main screen, select Boot Manager. Main Advance d Security Server Management Boot Options Boot Manager [Internal EFI Shell]   Figure 41. Setup Utility — Boot Manager Screen Display Table 38.
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Intel®Server Board S5500BC TPS BIOS Setup Utility 5.3.2.9 Exit Screen The Exit screen allows the user to choose whether to save or discard the configuration changes made on the other screens. It also allows the user to restore the server to the factory defaults or to save or restore them to set of user-defined default values. If Load Default Values is selected, the factory default settings (noted in bold in the tables in this chapter) are applied.
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BIOS Setup Utility Setup Item Save as User Default Values Intel®Server Board S5500BC TPS Help Text Save current BIOS Setup utility values as custom user default values. If needed, the user default values can be restored via the Load User Default Values option below. Comments User is prompted for confirmation. Note: Clearing the CMOS or NVRAM causes the user default values to be reset to the factory default values. Load User Default Values Load user default values. User is prompted for confirmation. 5.
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Intel®Server Board S5500BC TPS Connector / Header Locations and Pin-outs 6. Connector / Header Locations and Pin-outs 6.1 Board Connectors Table 41.
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Connector / Header Locations and Pin-outs Intel®Server Board S5500BC TPS 6.2 Power Connectors The main power supply connection has an SSI-compliant 2x12 pin connector (J9B3). In addition, there are two additional power related connectors:  One SSI-compliant 2x4 pin power connector (J7K1) , which provides 12 V power to the CPU Voltage Regulators and Memory.  One SSI-compliant 1x5 pin connector(J9C1), which provides I2C monitors to the power supply. The following tables define the connector pin-outs.
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Intel®Server Board S5500BC TPS Connector / Header Locations and Pin-outs Table 44. EPS12V 1x5 Connector (J9E1) Pin Signal Name Signal Name 1 SMB_PWR_3V3SB_CLK White 2 SMB_PWR_3V3SB_DAT Yellow 3 NC N/A 4 GND Black 5 3.3V SENSE+ Orange 6.3 Riser Card Slot The Intel® Sever Board S5500BC have one riser card slot (J4B2). The riser card slot supports one low-profile half-length PCI Express* 2.0 x8 add-in card. Table 45.
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Connector / Header Locations and Pin-outs Pin B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 Name PETxN4 GND GND PETxP5 PETxN5 GND GND PETxP6 PETxN6 GND GND PETxP7 PETxN7 GND PRSNT2# PE Strap Intel®Server Board S5500BC TPS Slot Name GND PERxP4 PERxN4 GND GND PERxP5 PERxN5 GND GND PERxP6 PERxN6 GND GND PERxP7 PERxN7 GND Pin A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 6.4 RMM3 Connector The Intel® Sever Board S5500BC provides a connector (J3C1) to support a RMM3 card.
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Intel®Server Board S5500BC TPS Connector / Header Locations and Pin-outs 6.5 SSI Front Panel Connector The Intel® Server Board S5500BC provides a 24-pin SSI control panel connector (J9E2) for use with a non-Intel chassis. Several LEDs, such as the power status LED, HDD LED, and LAN status LED, are provided on the front panel to provide a visual status. The following table provides the pin-out information for this connector. Table 47.
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Connector / Header Locations and Pin-outs Intel®Server Board S5500BC TPS Table 48. VGA Connector Pin-out (J7A1) Pin Signal Name 1 VGA_RED 2 VGA_GREEN 3 VGA_BLUE 4 RESERVED 5 GND 6 GND 7 GND 8 GND 9 5V 10 GND 11 RESERVED 12 DDCDAT 13 HSYNC 14 VSYNC 15 DDCCLK 6.6.2 SATA II Connectors The Intel® Server Board S5500BC provides six Serial ATA connectors (J1B4, J1B3, J1A2, J1B1, J1B2, and J2B1). Table 49.
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Intel®Server Board S5500BC TPS Connector / Header Locations and Pin-outs 6.6.3 Serial Port Connectors The Intel® Server Board S5500BC provides one external 9-pin Serial ‗A‘ port (J8A1) and one internal 9-pin Serial B port header (J9A1). Serial A is a standard DB-9 interface which is located on the rear I/O panel of the server board. The following tables define the pin-outs for each: Table 50.
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Connector / Header Locations and Pin-outs Intel®Server Board S5500BC TPS Table 52. External USB and GbE connector Pin-out (J5A1, J6A1) Pin 1 USB PWR Signal Name 2 USBP_1N 3 USBP_1P 4 GND 5 USB PWR 6 USB_0N 7 USB_0P 8 GND 9 TERM 10 MDI0P 11 MDI0N 12 MDI1P 13 MDI1N 14 MDI2P 15 MDI2N 16 MDI3P 17 MDI3N 18 GND 19 GRN_C 20 GRN_A 21 GRN_C/YEL_A 22 GRN_A/YEL_C Four ports are connected to the two 2x5 headers (J1A3, J2A2) on the Intel® Server Board S5500BC.
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Intel®Server Board S5500BC TPS Connector / Header Locations and Pin-outs 6.7 Fan Headers The Intel® Server Board S5500BC incorporates a system fan circuit that supports five SSI compliant 4-pin fan connectors. The two 4-pin fan connectors are for processor cooling fans: CPU_1 fan (J3K1) and CPU_2 fan (J7K2). The three 4-pin fan connectors are for system fans system fan 1, system fan 2, and system fan 3 (J3K2, J8K3, and J8B4). The pin configuration for each fan connector is identical.
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Connector / Header Locations and Pin-outs Intel®Server Board S5500BC TPS 6.8 SGPIO Header One 4-Pin SGPIO Connector (J1C1). Table 55. SGPIO connector Pin-out (J1C1) Pin 1 Signal Name SCLK 2 SLOAD 3 SDATAOUT0 4 SDATEOUT1 6.9 Chassis Intrusion Header A 2-pin Chassis intrusion header (J8B3) is provided. This is intended to support micro switches that close, making a connection to ground when the chassis is opened or removed.
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Intel®Server Board S5500BC TPS Connector / Header Locations and Pin-outs 6.11 SATA RAID Key Header Table 58. SATA connector Pin-out (J7B1) Pin 1 Signal Name GND 2 FM_ICH_RAID_KEY 3 GND 6.12 IPMB Header Table 59. IPMB Connector Pin-out (J8B1) Pin 1 Revision 1.
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Jumper Block Settings Intel®Server Board S5500BC TPS 7. Jumper Block Settings The Intel® Server Board S5500BC has several jumper blocks that you can use to configure, recover, or enable /disable specific features of the server board. Pin 1 on each jumper block is denoted by ―▼‖. Figure 44. Jumper Blocks 100 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Jumper Block Settings Table 60. Jumper Block Matrix Jumper Name J8C1: BMC Force Update Pins 1-2 What happens at system reset… BMC Firmware Force Update Mode – Disabled (Default) 2-3 BMC Firmware Force Update Mode – Enabled J2D1: Password Clear 1-2 These pins should have a jumper in place for normal system operation. (Default) 2-3 If these pins are jumpered, administrator and user passwords will be cleared on the next reset.
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Intel®Light-Guided Diagnostics Intel®Server Board S5500BC TPS 8. Intel®Light-Guided Diagnostics The Intel® Server Board S5500BC has several onboard diagnostic LEDs to assist in troubleshooting board-level issues. Functionality of the onboard LEDs is owned by the BMC and system BIOS. This section provides an overview of each LED including the location and a high level-usage description. 8.
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Intel®Server Board S5500BC TPS Intel®Light-Guided Diagnostics Table 61. System Status LED Indicator States Color Green State Solid on System Status OK Description Green blink Degraded System degraded:  Non-critical temperature threshold asserted.  Non-critical voltage threshold asserted.  Non-critical fan threshold asserted.  Fan redundancy lost, sufficient system cooling maintained. This does not apply to non-redundant systems.  Power supply predictive failure.  Power supply redundancy lost.
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Intel®Light-Guided Diagnostics Intel®Server Board S5500BC TPS Table 62. DIMM LEDs Indicator States LED Name DIMM#A1E1 fault (7 total) Voltage resources 5V Aux Color Status Description Amber On Corresponding DIMM Fault N/A Off Normal 8.4 Fan Fault LEDs The Intel® Server Board S5500BC has a fan fault LED associated with each fan header. In the event of a critical threshold event status, the BMC will light a fan fault LED.
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Intel®Server Board S5500BC TPS Power and Environmental Specifications 9. Power and Environmental Specifications 9.1 Intel® Server Board S5500BC Design Specifications Operating the server board at conditions beyond the specifications outlined in the following table may cause permanent damage to the system. Exposure to maximum conditions for extended periods may impact system reliability. Table 64.
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Power and Environmental Specifications Intel®Server Board S5500BC TPS Figure 45. Power Distribution Block Diagram 106 Intel order number: E42249-009 Revision 1.
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Intel®Server Board S5500BC TPS Power and Environmental Specifications 9.2.1 Output Power / Currents The following table defines power and current ratings for this 400W power supplies. The combined output power of all outputs shall not exceed the rated output power. The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions. Table 65. 400W Load Ratings +3.3 V Voltage Minimum Continuous 3.0 A Maximum Continuous 15 A +5 V 0A 10 A +12 V1 0.
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Power and Environmental Specifications Intel®Server Board S5500BC TPS Note: The grounding should be well designed to ensure passing the maximum allowed common mode noise levels. 9.2.4 Standby Outputs The 5 VSB output should be present when an AC input greater than the power supply turn on voltage is applied. 9.2.5 Remote Sense The power supply has remote sense return (ReturnS) to regulate out ground drops for all output voltages; +3.3V, +5V, +12V1, +12V2, -12V, and 5VSB.
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Intel®Server Board S5500BC TPS Power and Environmental Specifications Table 67. Voltage Regulation Limits Parameter + 3.3V Tolerance - 5% / +5% Minimum +3.14 Nominal +3.30 Maximum +3.46 Units Vrms + 5V - 5% / +5% +4.75 +5.00 +5.25 Vrms + 12V1,2 - 5% / +5% +11.40 +12.00 +12.60 Vrms - 12V - 10% / +10% -10.80 -12.00 -13.08 Vrms + 5VSB - 5% / +5% +4.75 +5.00 +5.25 Vrms 9.2.
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Power and Environmental Specifications Intel®Server Board S5500BC TPS with local sensing through the submission of bode plots. Closed-loop stability must be maintained at the maximum and minimum loads as applicable. 9.2.11 Common Mode Noise The common mode noise on any output should not exceed 350 mV peak-peak over the frequency band of 10 Hz to 30 MHz.
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Intel®Server Board S5500BC TPS Power and Environmental Specifications Table 71. Output Voltage Timing Item Description Tvout_rise Output voltage rise time from each main output. Tvout_on T vout_off Minimum 5.0 * Maximum Units 70 * msec All main outputs must be within regulation of each other within this time. 50 msec All main outputs must leave regulation within this time. 400 msec *The 5 VSB output voltage rise time shall be from 1.0 ms to 25.0 ms Figure 46.
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Power and Environmental Specifications Item Description Intel®Server Board S5500BC TPS Minimum Maximum Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on. 100 500 T pwok_off Delay from PWOK de-asserted to output voltages (3.3V, 5V, 12V, -12V) dropping out of regulation limits. 1 Tpwok_low Duration of PWOK in the de-asserted state during an off/on cycle using AC or the PSOn signal.
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Intel®Server Board S5500BC TPS Power and Environmental Specifications 9.2.16 Protection Circuits Protection circuits inside the power supply shall cause only the power supply‘s main outputs to shutdown. If the power supply latches off due to a protection circuit tripping, an AC cycle OFF for 15sec and a PSON# cycle HIGH for 1sec shall be able to reset the power supply. 9.2.17 Current Limit (OCP) The power supply shall have current limit to prevent the +3.
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Power and Environmental Specifications Intel®Server Board S5500BC TPS 9.2.19 Over Temperature Protection (OTP) The power supply will be protected against over temperature conditions caused by loss of fan cooling or excessive ambient temperature. In an OTP condition the PSU will shutdown. When the power supply temperature drops to within specified limits, the power supply shall restore power automatically, while the 5VSB remains always on.
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Intel®Server Board S5500BC TPS Regulatory and Certification Information 10. Regulatory and Certification Information WARNING To ensure regulatory compliance, you must adhere to the assembly instructions in this guide to ensure and maintain compliance with existing product certifications and approvals. Use only the described, regulated components specified in this guide.
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Regulatory and Certification Information Intel®Server Board S5500BC TPS 10.1.2 Product EMC Compliance – Class A Compliance Note: This product requires complying with Class A EMC requirements. However, Intel targets a 10 db margin to support customer enablement.
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Intel®Server Board S5500BC TPS Regulatory and Certification Information The server board complies with the following ecology regulatory requirements:  All materials, parts, and subassemblies must not contain restricted materials as defined in Intel’s Environmental Product Content Specification of Suppliers and Outsourced Manufacturers – http://supplier.intel.com/ehs/environmental.htm.
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Regulatory and Certification Information Intel®Server Board S5500BC TPS 10.2 Product Regulatory Compliance Markings The server board is provided with the following regulatory marks: Table 75.
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Intel®Server Board S5500BC TPS Regulatory Compliance China RoHS Marking Regulatory and Certification Information Region China Recycling Package Marking (Marked on packaging label) China Other Recycling Package Marking (Marked on packaging label) Other Recycling Package Marks Other Recycling Package Marking (Marked on packaging label) CA. Lithium Perchlorate insert Revision 1.8 Marking China Perchlorate Material – Special handling may apply. See www.dtsc.ca.
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Regulatory and Certification Information Intel®Server Board S5500BC TPS 10.3 Electromagnetic Compatibility Notices 10.3.1 FCC Verification Statement (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E.
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Intel®Server Board S5500BC TPS Regulatory and Certification Information 10.3.2 ICES-003 (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur: ―Appareils Numériques‖, NMB-003 édictée par le Ministre Canadian des Communications.
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Regulatory and Certification Information Intel®Server Board S5500BC TPS 10.3.5 BSMI (Taiwan) The BSMI Certification Marking and EMC warning is located on the outside rear area of the product. 10.3.6 RRL (Korea) Following is the RRL certification information for Korea. English translation of the notice above: 1. 2. 3. 4. 5. Type of Equipment (Model Name): On License and Product Certification No.: On RRL certificate.
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Intel®Server Board S5500BC TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips           When adding or removing components or peripherals from the server board, you must remove AC power. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off. Only Intel® Xeon® processor 5500 series with 95 W and less Thermal Design Power (TDP) are supported on this server board.
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Appendix B: Sensor Tables Intel®Server Board S5500BC TPS Appendix B: Sensor Tables This appendix lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information.
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Intel®Server Board S5500BC TPS  Appendix B: Sensor Tables Event Data This is the data included in an event message generated by the associated sensor. For threshold-based sensors, these abbreviations are used: R: Reading value T: Threshold value  Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors can be done manually or automatically.
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Appendix B: Sensor Tables Intel®Server Board S5500BC TPS Table 76. Integrated BMC Core Sensors Full Sensor Name Sensor # (Sensor name in SDR) Platform Applicability Sensor Type Event / Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S5500BC TPS Full Sensor Name Sensor # (Sensor name in SDR) Appendix B: Sensor Tables Platform Applicability Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status Assert / Deassert Readabl e Value / Offsets 06 – Redundant: degraded from fully redundant state. Degraded 07 – Redundant: Transition from non-redundant state.
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Appendix B: Sensor Tables Full Sensor Name Sensor # (Sensor name in SDR) Intel®Server Board S5500BC TPS Platform Applicability Sensor Type System Event Event / Reading Type Sensor Specific Event Offset Triggers 04 – PEF action 08h BB +1.1V IOH (BB +1.1V IOH) 10h All Voltage 02h Threshold 01h [u,l] [c,nc] BB +1.1V P1 Vccp (BB +1.1V P1 Vccp) 11h All Voltage 02h Threshold 01h [u,l] [c,nc] BB +1.1 P2 Vccp (BB +1.
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Intel®Server Board S5500BC TPS Full Sensor Name Appendix B: Sensor Tables Sensor # Platform Applicability Sensor Type Event / Reading Type Event Offset Triggers 19h All Voltage 02h Threshold 01h [u,l] [c,nc] 1Ah All Voltage 02h Threshold 01h [u,l] [c,nc] 1Bh All Voltage 02h Threshold 01h [u,l] [c,nc] 1Ch All Voltage 02h Threshold 01h [u,l] [c,nc] 20h All Temperature Threshold 01h 01h 21h All Temperature Threshold 01h 01h 22h All Temperature Threshold 01h 01h Proc
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Appendix B: Sensor Tables Full Sensor Name Sensor # (Sensor name in SDR) Fan Present Sensors (Fan x Present) 40h–45h Intel®Server Board S5500BC TPS Platform Applicability Sensor Type Event / Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S5500BC TPS Full Sensor Name Sensor # (Sensor name in SDR) Appendix B: Sensor Tables Platform Applicability Sensor Type Event / Reading Type Event Offset Triggers 06 – NonRedundant: degraded from fully redundant. Contrib.
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Appendix B: Sensor Tables Full Sensor Name Sensor # Platform Applicability Sensor Type Event / Reading Type 52h Chassisspecific Other Units Threshold 0Bh 01h 53h Chassisspecific Other Units Threshold 0Bh 01h 54h Chassisspecific Current Threshold 03h 01h 55h Chassisspecific Current Threshold 03h 01h 56h Chassisspecific Temperature Threshold 57h Chassisspecific 60h All (Sensor name in SDR) Power Supply 1 AC Power Input (PS/1 Power In) Power Supply 2 AC Power Input (PS/2 P
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Intel®Server Board S5500BC TPS Full Sensor Name Sensor # Platform Applicability 64h All 65h Dual processor only (Sensor name in SDR) Processor 1 Thermal Control % Appendix B: Sensor Tables (P1 Therm Ctrl %) Processor 2 Thermal Control % (P2 Therm Ctrl %) Processor 1 VRD Temp (P1 VRD Hot) Processor 2 VRD Temp (P2 VRD Hot) Catastrophic Error (CATERR) CPU Missing (CPU Missing) IOH Thermal Trip (IOH Thermal Trip) Revision 1.
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Appendix C: POST Error Messages and Handling Intel®Server Board S5500BC TPS Appendix C: POST Error Messages and Handling Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Intel®Server Board S5500BC TPS Appendix C: POST Error Messages and Handling Table 78. POST Error Messages and Handling Error Code 0012 CMOS date / time not set Error Message Major 0048 Password check failed Major 0108 Keyboard component encountered a locked error. Minor 0109 Keyboard component encountered a stuck key error. Minor 0113 Fixed Media The SAS RAID firmware can not run properly. The user should attempt to reflash the firmware. Major 0140 PCI component encountered a PERR error.
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Appendix C: POST Error Messages and Handling Intel®Server Board S5500BC TPS Error Code 8529 DIMM_E2 failed Self Test (BIST). Major 852A DIMM_F1 failed Self Test (BIST). Major 852B DIMM_F2 failed Self Test (BIST). Major 8540 DIMM_A1 Disabled. Major 8541 DIMM_A2 Disabled. Major 8542 DIMM_B1 Disabled. Major 8543 DIMM_B2 Disabled. Major 8544 DIMM_C1 Disabled. Major 8545 DIMM_C2 Disabled. Major 8546 DIMM_D1 Disabled. Major 8547 DIMM_D2 Disabled. Major 8548 DIMM_E1 Disabled.
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Intel®Server Board S5500BC TPS Appendix C: POST Error Messages and Handling Error Code 9246 Error Message Mouse component encountered a controller error. Minor Response 9266 Local Console component encountered a controller error. Minor 9268 Local Console component encountered an output error. Minor 9269 Local Console component encountered a resource conflict error. Minor 9286 Remote Console component encountered a controller error.
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Appendix C: POST Error Messages and Handling Intel®Server Board S5500BC TPS Table 79. POST Error Beep Codes Beeps 3 Error Message Memory error POST Progress Code Multiple Description System halted because a fatal error related to the memory was detected. The following Beep Codes are from the BMC, and are controlled by the Firmware team. They are listed here for convenience. 1-5-2-1 CPU: Empty slot / population error. N/A CPU sockets are populated incorrectly – CPU1 must be populated before CPU2.
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Intel®Server Board S5500BC TPS Appendix D: POST Code Diagnostic LED Decoder Appendix D: POST Code Diagnostic LED Decoder The BIOS executes platform configuration processes during the system boot. Each process is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST Code Diagnostic LEDs on the back edge of the server board. The Diagnostic LEDs identify the last POST process to be executed.
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Appendix D: POST Code Diagnostic LED Decoder Intel®Server Board S5500BC TPS Table 81. Diagnostic LED POST Code Decoder Diagnostic LED Decoder O = On, X=Off Checkpoint Upper Nibble Lower Nibble Description MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 Multi-use code – This POST Code is used in different contexts.
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Intel®Server Board S5500BC TPS Appendix D: POST Code Diagnostic LED Decoder Diagnostic LED Decoder O = On, X=Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 0x51h X O X O X X X O 0x52h X O X O X X O X 0x53h X O X O X X O O 0x54h X O X O X O X X 0x55h X O X O X O X O 0X56h X O X O X O O X 0x57h X O X O X O O O USB 0x58h X O X O O X X X 0x59h X O X O O X X O ATA/ATAPI/SATA 0x5Ah X O X O O X O X 0x5Bh X O X O O X O O SMBUS 0x5Ch X O X O O O X X 0x5Dh X O X
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Appendix D: POST Code Diagnostic LED Decoder Intel®Server Board S5500BC TPS Diagnostic LED Decoder O = On, X=Off Checkpoint Upper Nibble Lower Nibble Description MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED #7 #6 #5 #4 #3 #2 #1 #0 0xD3 O O X O X X O O Trying to boot device selection 3 0xD4 O O X O X O X X Trying to boot device selection 4 0xD5 Trying to boot device selection 5 X O X O O O X O 0xD6 O O X O X O O X Trying to boot device selection 6 0Xd7 O O X 0xD8 O O X O X O O O Trying to boo
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Intel®Server Board S5500BC TPS Appendix E: Intel®Server System SR1630BC Appendix E: Intel®Server System SR1630BC The Intel® Server System SR1630BC 1U server system is designed to support the Intel® Server Board S5500BC. The server board and the system have features designed to support the highdensity server market. For more information, refer to the Intel® Server System SR1630BC Technical Product Specification (TPS).
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Appendix F: Supported Intel®Server Chassis SC5650 and Intel®Server System SC5650BCDPIntel®Server Board S5500BC TPS Appendix F: Supported Intel®Server Chassis SC5650 and Intel®Server System SC5650BCDP The Intel® Entry Server Chassis SC5650 is a 5.2U pedestal chassis designed to support the Intel® Server Boards S5500BC.
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Intel®Server Board S5500BC TPS Glossary Glossary Term ACPI Advanced Configuration and Power Interface AP Application Processor APIC Advanced Programmable Interrupt Control ASIC Application Specific Integrated Circuit ASMI Advanced Server Management Interface BIOS Basic Input/Output System BIST Built-In Self Test BMC Baseboard Management Controller Bridge Circuitry connecting one computer bus to another, allowing an agent on one to access the other BSP Bootstrap Processor byte 8-bit qu
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Glossary Intel®Server Board S5500BC TPS Term IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024 KB MCH Memory Controller Hub MD2 Message Digest 2 – Hashing Algorithm MD5 Message Digest 5 – Hashing Algorithm – Higher
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Intel®Server Board S5500BC TPS Glossary Term SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Coordinated Universal Time VID Voltage Identification VRD Voltage Regulator Down Word 16-bit quantity ZIF Zero Insertion Force Revision 1.
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Reference Documents Intel®Server Board S5500BC TPS Reference Documents 148  Intel® S5500 Chipsets Server Board BIOS External Product Specification  Intel® S5500 Chipsets Server Board Baseboard Management Controller Core External Product Specification  Intel® Remote Management Module 2 Technical Product Specification  Intelligent Platform Management Interface (IPMI) 2.