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Intel

Server Boards S5520HC and

S5500HCV

Technical Product Specification

Intel order number E39529-009

Revision 1.2

July 2009

Enterprise Platforms and Services Division

Summary of content (192 pages)

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Intel® Server Boards S5520HC and S5500HCV Technical Product Specification Intel order number E39529-009 Revision 1.
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Revision History Intel® Server Boards S5520HC and S5500HCV TPS Revision History Date February 2008 Revision Number 0.1 Modifications Preliminary Draft March 2008 0.3 Content Update March 2008 0.5 Updated sections 2.1 and 3.2. April 2008 0.55 Updated product code and processor support related information. August 2008 0.6 Updated product code and memory support related information; S5500HCV DIMM slot population change; and Chassis Intrusion header location change. September 2008 0.
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Intel® Server Boards S5520HC and S5500HCV TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server Boards S5520HC and S5500HCV TPS Table of Contents 1. 2. Introduction .......................................................................................................................... 1 1.1 Chapter Outline........................................................................................................ 1 1.2 Server Board Use Disclaimer .................................................................................. 1 Overview ..........................
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Intel® Server Boards S5520HC and S5500HCV TPS 3.3.4 Publishing System Memory ................................................................................... 32 3.3.5 Memory Interleaving .............................................................................................. 32 3.3.6 Memory Test.......................................................................................................... 33 3.3.7 Memory Scrub Engine ...............................................................
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Table of Contents 4.2.2 Keyboard, Video, and Mouse (KVM) Redirection .................................................. 58 4.2.3 Media Redirection.................................................................................................. 58 4.2.4 Web Services for Management (WS-MAN) ........................................................... 59 4.2.5 Embedded Web server .......................................................................................... 60 4.2.
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Intel® Server Boards S5520HC and S5500HCV TPS 7.1.1 Clearing the CMOS.............................................................................................. 118 7.1.2 Clearing the Password......................................................................................... 118 7.2 Force BMC Update Procedure ............................................................................ 119 7.3 8. 9. Table of Contents BIOS Recovery Jumper ....................................................
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Table of Contents Intel® Server Boards S5520HC and S5500HCV TPS VCCI (Japan)...................................................................................................................... 141 BSMI (Taiwan).................................................................................................................... 141 RRL KCC (Korea)............................................................................................................... 142 CNCA (CCC-China) .............................
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Intel® Server Boards S5520HC and S5500HCV TPS List of Figures List of Figures Figure 1. Intel® Server Board S5520HC........................................................................................ 5 Figure 2. Intel® Server Board S5500HCV ..................................................................................... 5 Figure 3. Major Board Components.............................................................................................. 7 Figure 4. Mounting Hole Locations ..............
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List of Figures Intel® Server Boards S5520HC and S5500HCV TPS Figure 32. Setup Utility — Security Configuration Screen Display ............................................. 87 Figure 33. Setup Utility — Server Management Configuration Screen Display .......................... 89 Figure 34. Setup Utility — Console Redirection Screen Display ................................................ 91 Figure 35. Setup Utility — Server Management System Information Screen Display ................ 93 Figure 36.
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Intel® Server Boards S5520HC and S5500HCV TPS List of Tables List of Tables Table 1. IOH High-Level Summary ............................................................................................. 20 Table 2. Mixed Processor Configurations ................................................................................... 23 Table 3. Memory Running Frequency vs. Processor SKU.......................................................... 30 Table 4. Memory Running Frequency vs. Memory Population .........
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List of Tables Intel® Server Boards S5520HC and S5500HCV TPS Table 33. Setup Utility — Server Management System Information Fields ................................ 93 Table 34. Setup Utility — Boot Options Screen Fields ............................................................... 95 Table 35. Setup Utility — Add New Boot Option Fields .............................................................. 96 Table 36. Setup Utility — Delete Boot Option Fields ....................................................
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Intel® Server Boards S5520HC and S5500HCV TPS List of Tables Table 68. Server Board Jumpers (J1E6, J1E2, J1E4, J1E5, J1H1) ......................................... 117 Table 69. System Status LED................................................................................................... 124 Table 70. Server Board Design Specifications ......................................................................... 127 Table 71. MTBF Estimate ...............................................................
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List of Tables Intel® Server Boards S5520HC and S5500HCV TPS Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Server Boards S5520HC and S5500HCV. In addition, you can obtain design-level information for a given subsystem by ordering the External Product Specifications (EPS) for the specific subsystem.
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Overview 2. Intel® Server Boards S5520HC and S5500HCV TPS Overview The Intel® Server Boards S5520HC and S5500HCV are monolithic printed circuit boards (PCBs) with features designed to support the pedestal server markets. 2.1 Intel® Server Boards S5520HC and S5500HCV Feature Set Feature Processors Description ® ®  Support for one or two Intel Xeon Processor(s) 5500 series ® ®  4.8 GT/s, 5.86 GT/s, and 6.
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Intel® Server Boards S5520HC and S5500HCV TPS Feature Add-in Card Slots Overview Description  Intel Server Board S5520HC: Six expansion slots ®  One full-length/full-height PCI Express* Gen2 slot (x16 Mechanically, x8 Electrically)  Three full-length/full-height PCI Express* Gen2 x8 slots  One full-length/full-height PCI Express* Gen1 slot (x8 Mechanically, x4 Electrically) shared with SAS Module slot*.
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Overview Feature Server Management Intel® Server Boards S5520HC and S5500HCV TPS Description  Onboard ServerEngines* LLC Pilot II* Controller  Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant  Integrated Super I/O on LPC interface ®  Support for Intel Remote Management Module 3 ®  Intel Light-Guided Diagnostics on field replaceable units ®  Support for Intel System Management Software 3.
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Intel® Server Boards S5520HC and S5500HCV TPS Overview Server Board Layout Figure 1. Intel® Server Board S5520HC Figure 2. Intel® Server Board S5500HCV 2.1.1 Server Board Connector and Component Layout The following figure shows the layout of the server board. Each connector and major component is identified by a number or letter, and a description is given below the figure. Revision 1.
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Overview Callout A B C D E F G H Intel® Server Boards S5520HC and S5500HCV TPS Description Slot 1, 32-bit/33 MHz PCI, Keying for 5V and Universal Intel® RMM3 Slot Slot 2, PCI Express* x4 (x8 Mechanically) Low-profile USB Solid State Drive Header Slot 3, PCI Express* Gen2 x8 Slot 4, PCI Express* Gen2 x8 ® Slot 5, PCI Express* Gen2 x8 (Empty on Intel Server Board S5500HCV) Callout S5520HC: Slot 6, PCI Express* Gen2 x8 (x16 Description W System Fan 2 Header (6-pin) X Y Z AA BB System Fan 1 Header (6-
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Intel® Server Boards S5520HC and S5500HCV TPS Callout I J K L M N O P Description Mechanically) S5500HCV: Slot 6, PCI Express* Gen2 x4 (x16 Mechanically) Battery Back Panel I/O Ports Diagnostic and Identify LED’s System Fan 5 Header (4-pin) Power Connector for Processor 1 and Memory attached to Processor 1 Processor 1 Fan Header (4-pin) DIMM Sockets of Memory Channel A, B, and C Power Connector for Processor 2 and Memory attached to Processor 2 Overview Callout EE FF GG HH II Description HSBP_B SATA
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Overview 2.1.2 Intel® Server Boards S5520HC and S5500HCV TPS Server Board Mechanical Drawings Figure 4. Mounting Hole Locations Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS Overview Figure 5. Major Connector Pin-1 Locations (1 of 2) Revision 1.
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Overview Intel® Server Boards S5520HC and S5500HCV TPS Figure 6. Major Connector Pin-1 Locations (2 of 2) Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS Overview Figure 7. Primary Side Keep-out Zone (1 of 2) Revision 1.
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Overview Intel® Server Boards S5520HC and S5500HCV TPS Figure 8. Primary Side Keep-out Zone (2 of 2) Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS Overview Figure 9. Primary Side Air Duct Keep-out Zone Revision 1.
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Overview Intel® Server Boards S5520HC and S5500HCV TPS Figure 10. Primary Side Card-Side Keep-out Zone Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS Overview Figure 11. Second Side Keep-out Zone Revision 1.
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Overview 2.1.3 Intel® Server Boards S5520HC and S5500HCV TPS Server Board Rear I/O Layout The following drawing shows the layout of the rear I/O components for the server boards. Callou t A Description Callout Description System Status LED E B ID LED F C Diagnostics LED’s G Video NIC Port 1 (1 Gb, Default Management Port) USB Port 2 (top), 3 (bottom) NIC Port 2 (1 Gb) USB Port 0 (top), 1 (bottom) D Serial Port A Figure 12. Rear I/O Layout Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Boards S5520HC and S5500HCV is based on the Intel® 5520 / 5500 and ICH10R chipset. The chipset is designed for systems based on the Intel® Xeon® Processor 5500 Series in an FC-LGA 1366 Socket B package with Intel® QuickPath Interconnect (Intel® QPI) speed at 6.40 GT/s, 5.86 GT/s, and 4.80 GT/s.
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS Figure 13. Intel® Server Board S5520HC Functional Block Diagram Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture Figure 14. Intel® Server Board S5500HCV Functional Block Diagram Revision 1.
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Functional Architecture 3.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture For a detailed PCI Express* Slots definition in the Intel® Server Boards S5520HC and S5500HCV, see “3.5 PCI Subsystem.” 3.1.3 Enterprise South Bridge Interface (ESI) One x4 ESI link interface supporting PCI Express Gen1 (2.5 Gbps) transfer rate for connecting Intel® ICH10R in the Intel® Server Boards S5520HC and S5500HCV. 3.1.
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Functional Architecture 3.2 Intel® Server Boards S5520HC and S5500HCV TPS Processor Support The Intel® Server Boards S5520HC and S5500HCV support one or two Intel® Xeon® Processor 5500 Series with a 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 95 W. The server boards do not support previous generations of the Intel® Xeon® Processors. For a complete updated list of supported processors, see: http://support.intel.com/support/motherboards/server/S5520HC/.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture Table 2. Mixed Processor Configurations Error Processor family not identical Processor stepping mismatch Severity Halt Pause System Action The BIOS detects the error condition and responds as follows: – Logs the error into the system event log (SEL). – Alerts the Integrated BMC about the configuration error. – Does not disable the processor.
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Functional Architecture Error Intel® Server Boards S5520HC and S5500HCV TPS Severity Processor microcode missing Minor System Action The BIOS detects the error condition and responds as follows: – Logs the error into the SEL. – Does not disable the processor. – Displays “8180: Processor 0x microcode update not found” message in the Error Manager or on the screen. – The system continues to boot in a degraded state, regardless of the setting of POST Error Pause in Setup.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture The BIOS creates entries in the Multi-Processor Specification, Version 1.4 tables to describe multi-core processors. 3.2.8 Direct Cache Access (DCA) Direct Cache Access (DCA) is a system-level protocol in a multi-processor system to improve I/O network performance, thereby providing higher system performance. The basic idea is to minimize cache misses when a demand read is executed.
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Functional Architecture 3.3 Intel® Server Boards S5520HC and S5500HCV TPS Memory Subsystem The Intel® Xeon® Processor 5500 Series on the Intel® Server Boards S5520HC and S5500HCV are populated on CPU sockets. Each processor installed on the CPU socket has an integrated memory controller (IMC), which supports up to three DDR3 channels and groups DIMMs on the server boards into autonomous memory. 3.3.
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Intel® Server Boards S5520HC and S5500HCV TPS Server Board CPU Socket CPU 1 Intel® Server S5520HC Board CPU 2 DIMM Identifier A1 (Blue) A2 (Black) B1 (Blue) B2 (Black) C1 (Blue) C2 (Black) D1 (Blue) D2 (Black) E1 (Blue) E2 (Black) F1 (Blue) F2 (Black) Functional Architecture Channel / Slot Channel A, Slot 0 Channel A, Slot 1 Channel B, Slot 0 Channel B, Slot 1 Channel C, Slot 0 Channel C, Slot 1 Channel D, Slot 0 Channel D, Slot 1 Channel E, Slot 0 Channel E, Slot 1 Channel F, Slot 0 Channel F, Slo
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS Server Board CPU Socket CPU 1 Intel® Server S5500HCV Board CPU 2 DIMM Identifier A1 (Blue) A2 (Black) B1 (Blue) B2 (Black) C1 (Blue) C2 (Black) D1 (Blue) E1 (Blue) F1 (Blue) Channel / Slot Channel A, Slot 0 Channel A, Slot 1 Channel B, Slot 0 Channel B, Slot 1 Channel C, Slot 0 Channel C, Slot 1 Channel D, Slot 0 Channel E, Slot 0 Channel F, Slot 0 Figure 17. Intel® Server Board S5500HCV DIMM Slots Arrangement 3.3.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture Mixing memory type, size, speed and/or rank on this platform has not been validated and is not supported  Mixing memory vendors is not supported on this platform by Intel  Non-ECC memory is not supported and has not been validated in a server environment Both Intel® Server Board S5520HC and Intel® Server Board S5500HCV support the following DIMM and DRAM technologies:  RDIMMs: – Single-, Dual-, and Quad-Rank – x 4 or x8 DRAM with 1 G
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS Table 3. Memory Running Frequency vs. Processor SKU DIMM Type DDR3 800 DDR3 1066 DDR3 1333 800 800 800 800 Processor Integrated Memory Controller (IMC) Max. Frequency (Hz) 1066 800 1066 1066 1333 800 1066 1333 Memory Running Frequency (Hz) = Fastest Common Frequency of Processor IMC and Memory Table 4. Memory Running Frequency vs.
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Intel® Server Boards S5520HC and S5500HCV TPS DIMM Type DIMM Populated Per Channel Functional Architecture Memory Running Frequency (Y/N) 800MHz 1066MHz Command / Address Rate 1333MHz Ranks Per DIMM SR: Single-Rank DR: Dual-Rank QR: Quad-Rank ECC Description memory: 800MHz, 1066MHz, or 1333MHz. UDIMM 2 Y Y N w/ or w/o ECC 1N: One clock cycle for the DRAM commands arrive at the DIMMs to execute. 2N: Two clock cycles for the DRAM commands arrive at the DIMMs to execute. 2N Revision 1.
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Functional Architecture 3.3.4 Intel® Server Boards S5520HC and S5500HCV TPS Publishing System Memory The BIOS displays the “Total Memory” of the system during POST if the “Quiet Boot” is disabled in the BIOS Setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system. The BIOS also provides the total memory of the system in the BIOS setup (Main page and Advanced | Memory Configuration Page).
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture  Bank Interleaving – Interleave cache-line data between participant ranks.  Channel Interleaving – Interleave between channel when not in Mirrored Channel Mode.  Socket Interleaving – Interleaved memory can spread between both CPU sockets when NUMA mode is disabled, given both CPU sockets are populated and DDR3 DIMMs are installed in slots for both sockets. 3.3.6 Memory Test 3.3.6.
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Functional Architecture 3.3.8.2 Intel® Server Boards S5520HC and S5500HCV TPS Independent Channel Mode In the Independent Channel mode, you can populate multiple channels on any channel in any order. The Independent Channel mode provides less RAS capability but better DIMM isolation in case of errors. Moreover, it allows the best interleave mode possible and thereby increases performance and thermal characteristics.
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Intel® Server Boards S5520HC and S5500HCV TPS  Functional Architecture Optimization techniques used by the Intel® Xeon® Processor 5500 Series to maximize memory bandwidth In the Independent Channel mode, all the DDR3 channels operate independently. Slot-to-slot DIMM matching is not required across channels (for example, A1 and B1 do not have to match each other in terms of size, organization, and timing).
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS timing, technology and size, CPU 2 memory channels D, E, and F can have a different match of the parameters, channel RAS still functions. 13. The Minimal memory population possible is {DIMM_A1}. In this configuration, the system operates in the Independent Channel Mode. Mirrored Channel Mode is not possible. 14. The minimal population upgrade recommended for enabling CPU 2 socket is {DIMM_A1 and DIMM_D1}.
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Intel® Server Boards S5520HC and S5500HCV TPS  Functional Architecture N – Identifies the total number of DIMMs that constitute the given configuration. Table 5.
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Functional Architecture 3.3.11 Intel® Server Boards S5520HC and S5500HCV TPS Memory Error Handling The BIOS classifies memory errors into the following categories:  Correctable ECC errors: This correction could be the result of an ECC correction, a successfully retried memory cycle, or both.  Unrecoverable/Fatal ECC Errors: The ECC engine detects these errors but cannot correct them.
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Intel® Server Boards S5520HC and S5500HCV TPS 3.4 Functional Architecture ICH10R The ICH10R provides extensive I/O support. Functions and capabilities include:  PCI Express* Base Specification, Revision 1.1, support  PCI Local Bus Specification, Revision 2.3, support for 33-MHz PCI operations (supports up to four REQ#/GNT# pairs)  ACPI Power Management Logic Support, Revision 3.
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS   Intel® Embedded Server RAID Technology II Option ROM Intel® Embedded Server RAID Technology II drivers, most recent revision  At least two SATA hard disk drives 3.4.1.1.
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Intel® Server Boards S5520HC and S5500HCV TPS Storage Controller Storage Mode* Description Functional Architecture RAID Types and Levels Supported SW RAID 0/1/10 standard SW RAID 6 SATA Ports SW RAID 5 with optional AXXRAKSW5 Driver RAID Management Software RAID Software User’s Guide Compatible Backplane ESRTII Driver Microsoft Windows* and selected Linux* Versions only ® Intel RAID Web Console 2 ® Intel RAID Software User’s Guide * Select in BIOS Setup: “SATA Mode” Option on Advanced | Ma
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Functional Architecture 3.4.2 Intel® Server Boards S5520HC and S5500HCV TPS USB 2.0 Support The USB controller functionality integrated into the ICH10R provides the server boards with an interface for up to ten USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable.  Four external connectors are located on the back edge of the server boards.  One internal 2x5 header (J1D1) is provided, capable of supporting two optional USB 2.0 ports.
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Intel® Server Boards S5520HC and S5500HCV TPS 3.5 Functional Architecture PCI Subsystem The primary I/O buses for the Intel® Server Board S5520HC are PCI, PCI Express* Gen1, and PCI Express* Gen2 with six independent PCI bus segments. The primary I/O buses for the Intel® Server Board S5500HCV are PCI, PCI Express* Gen1, and PCI Express* Gen2 with five independent PCI bus segments. PCI Express* Gen1 and Gen2 are dual-simplex point-to-point serial differential low-voltage interconnects.
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Functional Architecture PCI Bus Segment PE9, PE10 Intel® Server Boards S5520HC and S5500HCV TPS Voltage 3.3 V Width x8 Speed 40 Gb/S 5520 IOH PCI Express* Ports Type PCI Express* Gen2 PCI I/O Card Slots x8 PCI Express* Gen2 throughput to Slot 3 (x8 mechanically) Table 9. Intel® Server Board S5500HCV PCI Bus Segment Characteristics PCI Bus Segment PCI32 Voltage 5V Width 32 bit Speed 33 MHz Type PCI PCI Slot 1 PCI I/O Card Slots 3.
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Intel® Server Boards S5520HC and S5500HCV TPS 3. Functional Architecture The type 2 riser card must connect the PCI Express* pin A50 with a 4.7K ohm resistor to pull up to 3.3 V. The following table provides the supported bus throughput for the given riser card used and the number of add-in cards installed. Table 11.
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Functional Architecture 3.6 Intel® Server Boards S5520HC and S5500HCV TPS Intel® SAS Entry RAID Module AXX4SASMOD (Optional Accessory) The Intel® Server Boards S5520HC and S5500HCV provide a Serial Attached SCSI (SAS) module slot (J2J1) for the installation of an optional Intel® SAS Entry RAID Module AXX4SASMOD. Once the optional Intel® SAS Entry RAID Module AXX4SASMOD is detected, the x4 PCI Express* links from the ICH10R to Slot 2 (x8 mechanically, x4 electrically) switches to the SAS module slot.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture Figure 19. Intel® SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 3.6.1 SAS RAID Support The BIOS Setup Utility provides drive configuration options on the Advanced | Mass Storage Controller Configuration setup page for the Intel® SAS Entry RAID Module AXX4SASMOD, some of which affect the ability to configure RAID.
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS Table 12. Intel® SAS Entry RAID Module AXX4SASMOD Storage Mode SW RAID = Intel® Embedded Server RAID Technology II (ESRTII) IT/IR RAID = IT/IR RAID, Entry Hardware RAID Storage Mode* Description RAID Types and Levels Supported Driver RAID Management Software RAID Software User’s Guide Compatible Backplane Native SAS pass through mode without RAID function.
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Intel® Server Boards S5520HC and S5500HCV TPS 3.7 Functional Architecture Baseboard Management Controller The Intel® Server Boards S5520HC and S5500HCV have an integrated BMC controller based on ServerEngines* Pilot II. The BMC controller is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management.
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS Figure 20. Integrated BMC Hardware 3.7.1 BMC Embedded LAN Channel The BMC hardware includes two dedicated 10/100 network interfaces. Interface 1: This interface is available from either of the available NIC ports in system that can be shared with the host. Only one NIC may be enabled for management traffic at any time. The default active interface is onboard NIC1.
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Intel® Server Boards S5520HC and S5500HCV TPS 3.8 Functional Architecture Serial Ports The Intel® Server Boards S5520HC and S5500HCV provide two serial ports: an external DB9 serial port and an internal DH-10 serial header. The rear DB9 serial A port is a fully-functional serial port that can support any standard serial device. Serial B is an optional port accessible through a 9-pin internal DH-10 header. You can use a standard DH-10 to DB9 cable to direct serial B to the rear of a chassis.
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Functional Architecture 3.11.1 Intel® Server Boards S5520HC and S5500HCV TPS Video Modes The integrated video controller supports all standard IBM* VGA modes. The following table shows the 2D modes supported for both CRT and LCD. Table 14. Video Modes 2D Video Mode Support 2D Mode 640 x 480 800 x 600 1024 x 768 1152 x 864 1280 x 1024 1440 x 900 1600 x 1200 3.11.
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Intel® Server Boards S5520HC and S5500HCV TPS Functional Architecture 3.12 Network Interface Controller (NIC) The Intel® Server Boards S5520HC and S5500HCV provide dual onboard LAN ports with support for 10/100/1000 Mbps operation. The two LAN ports are based on the onboard Intel® 82575EB controller, which is a single, compact component with two, fully-integrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports. The Intel® 82575EB controller provides a standard IEEE 802.
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Functional Architecture Intel® Server Boards S5520HC and S5500HCV TPS 3.13 ACPI Support The Intel® Server Boards S5520HC and S5500HCV support S0, S1, and S5 states. S1 is considered a sleep state. The Intel® Server Boards S5520HC and S5500HCV can wake up from S1 state using the USB devices in addition to the sources described in the following paragraph.
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Intel® Server Boards S5520HC and S5500HCV TPS 4. Platform Management Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot II. The onboard platform management subsystem consists of communication buses, sensors, and the system BIOS, and server management firmware. Figure 21 provides an illustration of the Server Management Bus (SMBUS) architecture as used on these server boards. 4.1 Feature Support 4.1.1 IPMI 2.
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Platform Management Intel® Server Boards S5520HC and S5500HCV TPS  Chassis intrusion detection (dependant on platform support)  Basic fan control using TControl version 2 SDRs  Fan redundancy monitoring and support  Power supply redundancy monitoring and support  Hot swap fan support  Acoustic management: Supports multiple fan profiles  Signal testing support: The BMC provides test commands for setting and getting platform signal states.
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Intel® Server Boards S5520HC and S5500HCV TPS 4.2 Platform Management Optional Advanced Management Feature Support This section explains the advanced management features supported by the BMC firmware. Table 13 lists basic and advanced feature support. Individual features may vary by platform. For more information, refer to Appendix C. Table 16. Basic and Advanced Management Features Feature IPMI 2.
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Platform Management 4.2.2 Intel® Server Boards S5520HC and S5500HCV TPS Keyboard, Video, and Mouse (KVM) Redirection The advanced management features include support for keyboard, video, and mouse redirection (KVM) over LAN. This feature is available remotely from the embedded web server as a Java* applet. The client system must have a Java Runtime Environment (JRE) Version 1.6 (JRE6) or later to run the KVM or media redirection applets.
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Intel® Server Boards S5520HC and S5500HCV TPS Platform Management administrators or users to boot the server or install software (including operating systems), copy files, update the BIOS, and so forth, or boot the server from this device. The following capabilities are supported:  The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are usable in parallel.
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Platform Management  Intel® Server Boards S5520HC and S5500HCV TPS Software Inventory Profile (FW Version) Note: WS-MAN features will be made available after production launch. 4.2.5 Embedded Web server The BMC provides an embedded web server for out-of-band management. User authentication is handled by IPMI user names and passwords.
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Intel® Server Boards S5520HC and S5500HCV TPS 4.3 Platform Management Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels.
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Platform Management 4.3.1 Intel® Server Boards S5520HC and S5500HCV TPS Memory Open and Closed Loop Thermal Throttling Open-Loop Thermal Throttling (OLTT) Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory bus, which reduces power consumption and thermal output. With OLTT, the system throttles in response to memory bandwidth demands instead of actual memory temperature.
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Intel® Server Boards S5520HC and S5500HCV TPS Platform Management BIOS fails to get the Thermal SDRs, then it uses the Memory Reference Code (MRC) default settings for the memory throttling settings. The BIOS Setup Utility provides options to set the fan profile or operating mode the platform will operate under. Each operating mode has a predefined profile for which specific platform targets are configured, which in turn determines how the system fans operate to meet those targets.
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Platform Management 4.3.2.3.1 Intel® Server Boards S5520HC and S5500HCV TPS Performance Mode (Default) With the platform running in Performance mode (Default), several platform control algorithm variables are set to enhance the platform’s capability of operating at maximum performance targets for the given system. In doing so, the platform is programmed with higher fan speeds at lower ambient temperatures.
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Intel® Server Boards S5520HC and S5500HCV TPS 4.4 Platform Management Intel® Intelligent Power Node Manager Intel® Intelligent Power Node Manager is a platform (system)-level solution that provides the system with a method of monitoring power consumption and thermal output, and adjusting system variables to control those factors. The BMC supports Intel® Intelligent Power Node Manager specification version 1.5.
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Platform Management Intel® Server Boards S5520HC and S5500HCV TPS Figure 21. SMBUS Block Diagram Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS 5. BIOS Setup Utility 5.1 Logo / Diagnostic Screen BIOS Setup Utility The Logo / Diagnostic Screen displays in one of two forms:   If Quiet Boot is enabled in the BIOS setup, a logo splash screen is displayed. By default, Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press to hide the logo and display the diagnostic screen.
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BIOS Setup Utility 5.3.1 Intel® Server Board S5520HC / S5500HCV TPS Operation The BIOS Setup has the following features:  Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® server board BIOS is only available in English.  Console Redirection - The BIOS Setup is functional via console redirection over various terminal emulation standards.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Each Setup menu page contains a number of features. Each feature is associated with a value field except those used for informative purposes. Each value field contains configurable parameters. Depending on the security option selected and in effect by the password, a menu feature’s value may or may not change. If a value cannot be changed, its field is made inaccessible and appears grayed out. Table 19.
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BIOS Setup Utility Key Option Save and Exit Intel® Server Board S5520HC / S5500HCV TPS Description Pressing causes the following message to display: Save configuration and reset? Yes No If “Yes” is highlighted and is pressed, all changes are saved and the Setup is exited. If “No” is highlighted and is pressed, or the key is pressed, the user is returned to where they were before was pressed without affecting any existing values. 5.3.1.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.1 BIOS Setup Utility Main Screen Unless an error occurred, the Main screen is the first screen displayed when the BIOS Setup is entered. If an error occurred, the Error Manager screen displays instead. Main Advanced Security Server Management Boot Options Boot Manager Logged in as Platform ID System BIOS Version S5500.86B.xx.yy.
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BIOS Setup Utility Setup Item Memory Intel® Server Board S5520HC / S5500HCV TPS Options Help Text Size Information only. Displays the total physical memory installed in the system, in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs. Enabled Disabled [Enabled] – Display the logo screen during POST. POST Error Pause Enabled Disabled [Disabled] – Display the diagnostic screen during POST.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.2 BIOS Setup Utility Advanced Screen The Advanced screen provides an access point to configure several options. On this screen, the user selects the option they must configure. Configurations are performed on the selected screen and not directly on the Advanced screen. To access this screen from the Main screen, press the right arrow until the Advanced screen is selected.
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BIOS Setup Utility 5.3.2.2.1 Intel® Server Board S5520HC / S5500HCV TPS Processor Configuration Screen The Processor screen allows the user to view the processor core frequency, system bus frequency, and to enable or disable several processor options. This screen also allows the user to view information about a specific processor. To access this screen from the Main screen, select Advanced > Processor.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 22. Setup Utility — Processor Configuration Screen Fields Setup Item Options Help Text Comments Processor ID Information only. Processor CPUID Processor Frequency Information only. Current frequency of the processor. Microcode Revision Information only. Revision of the loaded microcode. L1 Cache RAM Information only. Size of the Processor L1 Cache. L2 Cache RAM Information only.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Setup Item Options Help Text Intel® Virtualization Technology Enabled Disabled Intel® Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions. Note: A change to this option requires the system to be powered off and then back on before the setting takes effect.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.2.2 BIOS Setup Utility Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed. This screen also allows the user to open the Configure Memory RAS and Performance screen. To access this screen from the Main screen, select Advanced > Memory.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Table 23. Setup Utility — Memory Configuration Screen Fields Setup Item Total Memory Options Help Text Comments Information only. The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB. Effective Memory Information only. The amount of memory available to the operating system in MB or GB.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5.3.2.2.2.1 Configure Memory RAS and Performance Screen The Configure Memory RAS and Performance screen allows the user to customize several memory configuration options, such as whether to use Memory Mirroring. To access this screen from the Main screen, select Advanced > Memory > Configure Memory RAS and Performance.
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BIOS Setup Utility 5.3.2.2.3 Intel® Server Board S5520HC / S5500HCV TPS Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA/SAS controller when it is present on the baseboard module card of an Intel system. To access this screen from the Main menu, select Advanced > Mass Storage.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 25. Setup Utility — Mass Storage Controller Configuration Screen Fields Setup Item Intel® Entry SAS RAID Module Options Enabled Disabled Help Text Enabled or Disable the Intel® SAS Entry RAID Module Comments Unavailable if the SAS Module (AXX4SASMOD) is not present.
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BIOS Setup Utility 5.3.2.2.4 Intel® Server Board S5520HC / S5500HCV TPS Serial Ports Screen The Serial Ports screen allows the user to configure the Serial A [COM 1] and Serial B [COM2] ports. To access this screen from the Main screen, select Advanced > Serial Port. Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Figure 28.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.2.5 BIOS Setup Utility USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Table 27. Setup Utility — USB Controller Configuration Screen Fields Setup Item Detected USB Devices Options Help Text Comments Information only. Shows the number of USB devices in the system. USB Controller Enabled Disabled [Enabled] - All onboard USB controllers are turned on and accessible by the OS. [Disabled] - All onboard USB controllers are turned off and inaccessible by the OS.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.2.6 BIOS Setup Utility PCI Screen The PCI Screen allows the user to configure the PCI add-in cards, onboard NIC controllers, and video options. To access this screen from the Main screen, select Advanced > PCI.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Setup Item Onboard NIC2 ROM Options Enabled Disabled Help Text If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC2 cannot be used to boot or wake the system. Onboard NIC iSCSI ROM Enabled Disabled If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC1 and NIC2 cannot be used to boot or wake the system.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 29. Setup Utility — System Acoustic and Performance Configuration Screen Fields Setup Item Set Throttling Mode Options Auto CLTT OLTT Altitude 300m or less 301m-900m 901m-1500m Higher than 1500m Help Text [Auto] – Auto Throttling mode. [CLTT] – Closed Loop Thermal Throttling Mode. [OLTT] – Open Loop Thermal Throttling Mode. [300m or less] (980ft or less) Comments Optimal performance setting near sea level.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Table 30. Setup Utility — Security Configuration Screen Fields Setup Item Administrator Password Status Options Help Text Comments Information only. Indicates the status of the administrator password. User Password Status Set Administrator Password [123aBcD] Administrator password is used to control change access in BIOS Setup Utility. Only alphanumeric characters can be used.
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Intel® Server Boards S5520HC and S5500HCV TPS Setup Item Options TPM Administrative No Operation Control** Turn On Turn Off Clear Ownership BIOS Setup Utility Help Text [No Operation] - No changes to current state. [Turn On] - Enables and activates TPM. [Turn Off] - Disables and deactivates TPM. [Clear Ownership] - Removes the TPM ownership authentication and returns the TPM to a factory default state. Note: The BIOS setting returns to [No Operation] on every boot cycle by default.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Table 31. Setup Utility — Server Management Configuration Screen Fields Setup Item Assert NMI on SERR Options Enabled Disabled Help Text On SERR, generate an NMI and log an error. Note: [Enabled] must be selected for the Assert NMI on PERR setup option to be visible. Assert NMI on PERR Enabled Disabled On PERR, generate an NMI and log an error. Note: This option is only active if the Assert NMI on SERR option is [Enabled] selected.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.4.1 BIOS Setup Utility Console Redirection Screen The Console Redirection screen allows the user to enable or disable console redirection and configure the connection options for this feature. To access this screen from the Main screen, select Server Management > Console Redirection. Server Management Console Redirection Console Redirection Disabled / Serial Port A / Serial Port B Flow Control None / RTS/CTS Baud Rate 9.6k / 19.2k / 38.4k / 57.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Table 32. Setup Utility — Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial Port A Serial Port B Help Text Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. [Serial Port B] - Configure serial port B for console redirection.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.5 BIOS Setup Utility Server Management System Information Screen The Server Management System Information screen allows the user to view part numbers, serial numbers, and firmware revisions. To access this screen from the Main screen, select Server Management > System Information.
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BIOS Setup Utility 5.3.2.6 Intel® Server Board S5520HC / S5500HCV TPS Boot Options Screen The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the desired boot device. To access this screen from the Main screen, select Boot Options.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 34. Setup Utility — Boot Options Screen Fields Setup Item Boot Timeout Options 0 - 65535 Help Text The number of seconds the BIOS should pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup utility. Valid values are 0-65535. Zero is the default. A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS If all types of bootable devices are installed in the system, then the default boot order is: 1. 2. 3. 4. 5. 6. CD/DVD-ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV (Boot Entry Vector) Device EFI Shell and EFI Boot paths 5.3.2.6.1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.6.2 BIOS Setup Utility Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order. Note that while you can delete the Internal EFI Shell in this screen, it is restored to the Boot Order on the next reboot. You cannot permanently delete the Internal EFI Shell. To access this screen from the Main screen, select Boot Options > Delete Boot Options.
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BIOS Setup Utility 5.3.2.6.3 Intel® Server Board S5520HC / S5500HCV TPS Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks. To access this screen from the Main screen, select Boot Options > Hard Disk Order. Boot Options Hard Disk #1 < Available Hard Disks > Hard Disk #2 < Available Hard Disks > Figure 39. Setup Utility — Hard Disk Order Screen Display Table 37.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 38. Setup Utility — CDROM Order Fields Setup Item CDROM #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. CDROM #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position. 5.3.2.6.5 Floppy Order Screen Comments The Floppy Order screen allows the user to control the floppy drives.
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BIOS Setup Utility 5.3.2.6.6 Intel® Server Board S5520HC / S5500HCV TPS Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices. To access this screen from the Main screen, select Boot Options > Network Device Order. Boot Options Network Device #1 Network Device #2 Figure 42. Setup Utility — Network Device Order Screen Display Table 40.
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Intel® Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 41. Setup Utility — BEV Device Order Fields Setup Item BEV Device #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. BEV Device #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position. 5.3.2.
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BIOS Setup Utility 5.3.2.8 Intel® Server Board S5520HC / S5500HCV TPS Error Manager Screen The Error Manager screen displays any errors encountered during POST. Error Manager ERROR CODE Exit SEVERITY INSTANCE Figure 45. Setup Utility — Error Manager Screen Display Table 43. Setup Utility — Error Manager Screen Fields Setup Item Displays System Errors Options Help Text Comments Information only. Displays errors that occurred during POST. Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS 5.3.2.9 BIOS Setup Utility Exit Screen The Exit screen allows the user to choose whether to save or discard the configuration changes made on the other screens. It also allows the user to restore the server to the factory defaults or to save or restore them to the set of user-defined default values. If Load Default Values is selected, the factory default settings (noted in bold in the tables in this chapter) are applied.
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BIOS Setup Utility Intel® Server Board S5520HC / S5500HCV TPS Setup Item Save as User Default Values Help Text Save current BIOS Setup utility values as custom user default values. If needed, the user default values can be restored via the Load User Default Values option below. Note: Clearing the CMOS or NVRAM does not cause the User Default values to be reset to the factory default values. Comments User prompted for confirmation. Load User Default Values Load user default values.
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Intel® Server Boards S5520HC and S5500HCV TPS Connector / Header Locations and Pin-outs 6. Connector / Header Locations and Pin-outs 6.1 Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen. Table 45.
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Connector / Header Locations and Pin-outs Connector Quantity Intel® Server Board S5520HC / S5500HCV TPS Reference Designators Connector Type Pin Count Serial ATA 6 J1G1, J1G4, J1G5, J1E3, J1F1, J1F4 Header 7 HSBP 2 J1F5, J1G3 Header 4 SATA SGPIO 1 J1G2 Header 4 LCP/IPMB 1 J1G6 Header 4 Configuration jumpers 4 J1E6 (CMOS Clear), J1E2 (ME Force Update), J1E4 (Password Clear), J1E5 Jumper (BIOS Recovery), J1H1 (BMC Force Update), 3 HDD Led 1 J1E1 2 Header * Empty on Intel® S
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Intel® Server Boards S5520HC and S5500HCV TPS Connector / Header Locations and Pin-outs Table 47. CPU 1 Power Connector Pin-out (J9A1) Pin Signal Color 1 GND of Pin 5 Black 2 GND of Pin 6 Black 3 GND of Pin 7 Black 4 GND of Pin 8 Black 5 +12 Vdc CPU1 Yellow / black 6 +12 Vdc CPU1 Yellow / black 7 +12 Vdc DDR3_CPU1 Yellow / black 8 +12 Vdc DDR3_CPU1 Yellow / black Table 48.
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Connector / Header Locations and Pin-outs 6.3 Intel® Server Board S5520HC / S5500HCV TPS System Management Headers Intel® Remote Management Module 3 Connector 6.3.1 A 34-pin Intel® RMM3 connector (J1C1) is included on the server boards to support the optional Intel® Remote Management Module 3. These server boards do not support third-party management cards.
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Intel® Server Boards S5520HC and S5500HCV TPS 6.3.3 Connector / Header Locations and Pin-outs HSBP Header Table 52. HSBP Header Pin-out (J1F5, J1G3) Pin 6.3.4 Signal Name Description 1 SMB_IPMB_5V_DAT BMC IMB 5 V Data Line 2 GND Ground 3 SMB_IPMB_5V_CLK BMC IMB 5V Clock Line 4 P5V – HSBP_A GND – HSBP_B +5 V for HSBP A Ground for HSBP B SGPIO Header Table 53. SGPIO Header Pin-out (J1G2) Pin 1 2 3 4 6.
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Connector / Header Locations and Pin-outs Intel® Server Board S5520HC / S5500HCV TPS SOR 23 6.5 6.5.1 Temperature Sensor NMI Button FP_NMI_BTN_N 24 N LED - NIC2_LINK_LED_ N NIC 2 Link LED - I/O Connectors VGA Connector The following table details the pin-out definition of the VGA connector (J7A1) that is part of the stacked video / serial port A connector. Table 55. VGA Connector Pin-out (J7A1) Pin 6.5.
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Intel® Server Boards S5520HC and S5500HCV TPS Pin Connector / Header Locations and Pin-outs Signal Name 9 NIC_A_MDI0P 10 NIC_A_MDI0N 11 NIC_LINKA_1000_N (LED 12 NIC_LINKA_100_N (LED) 13 NIC_ACT_LED_N 14 NIC_LINK_LED_N 15 GND 16 GND Revision 1.
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Connector / Header Locations and Pin-outs 6.5.3 Intel® Server Board S5520HC / S5500HCV TPS SATA Connectors The server boards provide up to six SATA connectors: SATA-0 (J1G5), SATA-1 (J1G4), SATA2 (J1G1), SATA-3 (J1F4), SATA-4 (J1F1), and SATA-5 (J1E3). The pin configuration for each connector is identical and defined in the following table. Table 57. SATA / SAS Connector Pin-out (J1E3, J1G1, J1G4, J1G5, J1F1, J1F4) Pin 6.5.
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Intel® Server Boards S5520HC and S5500HCV TPS Pin 39 6.5.5 Name Connector / Header Locations and Pin-outs Pin GND 40 Name PE_ICH10_SAS_SW_RXP3 41 PE_ICH10_SAS_SW_RXN3 42 GND 43 GND 44 CLK_100M_SAS_DP 45 CLK_100M_SAS_DN 46 GND 47 GND 48 P3V3 49 P3V3 50 P3V3 Serial Port Connectors The server boards provide one external DB9 Serial A port (J8A1) and one internal 9-pin Serial B header (J1B1). The following tables define the pin-outs. Table 59.
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Connector / Header Locations and Pin-outs Intel® Server Board S5520HC / S5500HCV TPS Table 61. External USB Connector Pin-out (J5A1, J6A1) Pin Signal Name Description 1 USB_OC_5VSB USB_PWR 2 USB_PN DATAL0 (Differential data line paired with DATAH0) 3 USB_PP DATAH0 (Differential data line paired with DATAL0) 4 GND Ground Two 2x5 connectors on the server boards (J1D1, J1D2) provide support for four additional USB ports. J1D2 is recommended for front panel USB ports. Table 62.
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Intel® Server Boards S5520HC and S5500HCV TPS Connector / Header Locations and Pin-outs Table 64.
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Connector / Header Locations and Pin-outs Intel® Server Board S5520HC / S5500HCV TPS 1 Ground GND Ground is the power supply ground 2 12V Power Power supply 12 V 3 Fan Tach In FAN_TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM Out FAN_PWM signal to control fan speed Table 67.
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Intel® Server Boards S5520HC and S5500HCV TPS 7. Jumper Blocks Jumper Blocks The server boards have several 3-pin jumper blocks that you can use to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 47. Jumper Blocks (J1E2, J1E4, J1E5, J1E6, J1H1) Table 68.
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Jumper Blocks Intel® Server Board S5520HC / S5500HCV TPS Jumper Name J1H1: Force Update 7.1 BMC Pins 1-2 2-3 System Results BMC Firmware Force Update Mode – Disabled (Default) BMC Firmware Force Update Mode – Enabled CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1E6) and Password Reset (J1E4) recovery features are designed to achieve the desired operation with minimum system down time.
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Intel® Server Boards S5520HC and S5500HCV TPS 7.2 Jumper Blocks Force BMC Update Procedure When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event the BMC firmware update process fails due to the BMC not being in the proper update state, the server boards provide a Force BMC Update jumper (J1H1) that forces the BMC into the proper update state.
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Jumper Blocks Intel® Server Board S5520HC / S5500HCV TPS 7. After successful completion of the BIOS recovery, the “BIOS has been updated successfully” message displays. 8. Power down the system and remove the AC power cord. 9. Open the server chassis. 10. Move the BIOS recovery jumper (J1E5) from the “enabled” position (covering pins 2 and 3) to the “disabled” position (covering pins 1 and 2). 11. Close the server chassis. 12. Reconnect the AC power cord and power up the server.
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Intel® Server Boards S5520HC and S5500HCV TPS 8. Intel® Light Guided Diagnostics Intel® Light Guided Diagnostics Both server boards have several onboard diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description of the location and function of each LED on the server boards. 8.1 5-volt Stand-by LED Several server management features of these server boards require a 5-V stand-by voltage supplied from the power supply.
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Intel® Light Guided Diagnostics 8.2 Intel® Server Board S5520HC / S5500HCV TPS Fan Fault LED’s Fan fault LEDs are present for the two CPU fans and the one rear system fan. The fan fault LEDs illuminate when the corresponding fan has fault. Figure 49. Fan Fault LED’s Location Revision 1.
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Intel® Server Boards S5520HC and S5500HCV TPS 8.3 Intel® Light Guided Diagnostics System ID LED and System Status LED The server boards provide LEDs for both system ID and system status. These LEDs are located in the rear I/O area of the server board as shown in the following figure. A. B. System ID LED System Status LED Figure 50.
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Intel® Light Guided Diagnostics  Intel® Server Board S5520HC / S5500HCV TPS By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either blink nlue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off. The bi-color (green / amber) System Status LED operates as follows: Table 69. System Status LED Color State Criticality Green Solid on System OK Description System booted and ready.
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Intel® Server Boards S5520HC and S5500HCV TPS 8.4 Intel® Light Guided Diagnostics DIMM Fault LEDs The server boards provide memory fault LED for each DIMM socket. These LEDs are located as shown in the following figure. The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs. * D2, E2, and F2 DIMM slot and Fault LED’s are empty in Intel® Server Board S5500HCV Figure 51. DIMM Fault LED’s Location Revision 1.
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Intel® Light Guided Diagnostics 8.5 Intel® Server Board S5520HC / S5500HCV TPS Post Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server boards in the rear I/O area of the server boards by the serial A connector. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number.
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Intel® Server Boards S5520HC and S5500HCV TPS Design and Environmental Specifications 9. Design and Environmental Specifications 9.1 Intel® Server Boards S5520HC and S5500HCV Design Specifications Operation of the Intel® Server Boards S5520HC and/or S5500HCV at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 70.
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Design and Environmental Specifications Intel® Server Board S5520HC / S5500HCV TPS   Operating Environment: Ground Benign, Controlled Duty Cycle: 100%  Quality Level: II Table 71. MTBF Estimate S5520HC MTBF (hours) 79,000 99,000 124,000 158,000 201,000 S5500HCV MTBF (hours) 89,000 111,000 140,000 178,000 227,000 Ambient Air Temperature (ºC) 45 40 35 30 25 Air Temp. at Board for 10(ºC) rise (ºC) 55 50 45 40 35 Revision 1.
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Intel® Server Board S5520HC / S5500HCV TPS 9.3 Design and Environmental Specifications Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel® Server Boards S5520HC and S5500HCV including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on these server boards. Figure 53. Power Distribution Block Diagram Revision 1.
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Design and Environmental Specifications 9.3.1 Intel® Server Board S5520HC / S5500HCV TPS Processor Power Support The server boards support the Thermal Design Power (TDP) guideline for Intel® Xeon® processors. The Flexible Motherboard Guidelines (FMB) were also followed to determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and TCASE for the compatible Intel® Xeon® Processor 5500 series.
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Intel® Server Board S5520HC / S5500HCV TPS 9.4.1 Design and Environmental Specifications Grounding The output ground of the pins of the power supply provides the output power return path. The output connector ground pins are connected to the safety ground (power supply enclosure). 9.4.2 Stand-by Outputs The 5 VSB output should be present when an AC input is greater than the power supply turn-on voltage is applied. 9.4.
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Design and Environmental Specifications 9.4.4 Intel® Server Board S5520HC / S5500HCV TPS Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple / noise. All outputs are measured with reference to the return remote sense signal (ReturnS). The +12 V3, +12 V4, –12 V and 5 VSB outputs are measured at the power supply connectors referenced to ReturnS. The +3.
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Intel® Server Board S5520HC / S5500HCV TPS 9.4.6 Design and Environmental Specifications Capacitive Loading The power supply should be stable and meet all requirements within the following capacitive loading range. Table 76. Capacitive Loading Conditions 9.4.7 Output Minimum Maximum Units +3.
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Design and Environmental Specifications Intel® Server Board S5520HC / S5500HCV TPS Table 78. Output Voltage Timing Item Description Minimum 5.0 1 Tvout_rise Output voltage rise time from each main output. Tvout_rise All main outputs must be within regulation of each other within this N/A time. Tvout_rise All main outputs must leave regulation within this time. 1. The 5 VSB output voltage rise time is from 1.
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Intel® Server Board S5520HC / S5500HCV TPS Design and Environmental Specifications Table 79. Turn On/Off Timing Item Description Minimum Maximum Units Tsb_on_delay Delay from AC being applied to 5 VSB being within regulation. N/A 1500 ms Tac_on_delay Delay from AC being applied to all output voltages being within N/A regulation. 2500 Tvout_holdup Time all output voltages stay within regulation after loss of AC.
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Design and Environmental Specifications 9.4.9 Intel® Server Board S5520HC / S5500HCV TPS Residual Voltage Immunity in Stand-by Mode The power supply should be immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from stand-by output) up to 500 mV. There should be no additional heat generated or stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously.
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Intel® Server Board S5520HC / S5500HCV TPS Regulatory and Certification Information 10. Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations, before computer integration, make sure that the chassis, power supply, and other modules have passed EMC testing using a server board with a microprocessor from the same family (or higher) and operating at the same (or higher) speed as the microprocessor used on this server board.
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Regulatory and Certification Information      10.1.3          Intel® Server Board S5520HC / S5500HCV TPS BSMI CNS13438 Emissions (Taiwan) RRL Notice No.
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Intel® Server Board S5520HC / S5500HCV TPS Regulatory and Certification Information 10.
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Regulatory and Certification Information Intel® Server Board S5520HC / S5500HCV TPS Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
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Intel® Server Board S5520HC / S5500HCV TPS Regulatory and Certification Information ICES-003 (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe A prescrites dans lanorme sur le matériel brouilleur: “Apparelis Numériques”, NMB-003 édictee par le Ministre Canadian des Communications.
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Regulatory and Certification Information Intel® Server Board S5520HC / S5500HCV TPS RRL KCC (Korea) CNCA (CCC-China) This CCC Certification Marking and EMC warning is located on the outside rear area of the product. 10.4 Product Ecology Change (EU RoHS) Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC.
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Intel® Server Board S5520HC / S5500HCV TPS Regulatory and Certification Information  EFUP for Intel server products has been determined as 20 years. Below is an example of EFUP mark applied to Intel server products. CRoHS Substance Tables: China CRoHS requires products to be provided with controlled substance information. Intel understands the end-seller (entity placing product into market place) is responsible for providing the controlled substance information.
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Regulatory and Certification Information Intel® Server Board S5520HC / S5500HCV TPS Revision 1.
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Intel® Server Board S5520HC / S5500HCV TPS Regulatory and Certification Information 10.6 China Packaging Recycle Marks (or GB18455-2001) Intel EPSD has the following ecological compliances: Cardboard and fiberboard packaging will be marked as recyclable in China. China Packaging Recycling Marks is required on retail packaging to be marked as recyclable using China’s recycling logo.
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Appendix A: Integration and Usage Tips Intel® Server Board S5520HC / S5500HCV TPS Appendix A: Integration and Usage Tips  Prior to adding or removing components or peripherals from the server board, you must remove the AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.  This server board supports Intel® Xeon® Processor 5500 Series only. This server board does not support previous generation Intel® Xeon® processors.
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Intel® Server Board S5520HC / S5500HCV TPS  Appendix A: Integration and Usage Tips device SEL event, There are multiple means to dump the PCI map.
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Appendix B: Compatible Intel® Server Chassis Intel® Server Board S5520HC / S5500HCV TPS Appendix B: Compatible Intel® Server Chassis Refer to the following table for the compatible Intel® Server Chassis of Intel® Server Boards S5520HC and S5500HCV: Passive tower processor heatsink(s) (product code: FXXRGTHSINK) is required when installing the Intel® Server Board S5520HC or S5500HCV in the Intel® Server Chassis SC5600LX.
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Intel® Server Board S5520HC / S5500HCV TPS S5520HC S5500HCV Chassis SKU Appendix B: Compatible Intel® Server Chassis Heatsink Includes Intel® Thermal Solution STS100C (w/ fan, Active mode) Intel® Thermal Solution STS100A (Active) BXSTS100C BXSTS100A FXXRGTHSINK (Passive Tower Heatsink) Chassis Boxed Product Code FXXRGTHSINK Note: Must install active processor heatsink with the airflow direction as shown in the following figure when installing in a compatible Intel® Server Chassis. Revision 1.
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Appendix B: Compatible Intel® Server Chassis Intel® Server Board S5520HC / S5500HCV TPS Figure 56. Active Processor Heatsink Installation Requirement Revision 1.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix C: BMC Sensor Tables Appendix C: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Appendix C: BMC Sensor Tables  Intel® Server Board S5520HC / S5500HCV TPS Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix C: BMC Sensor Tables Table 81.
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S5520HC / S5500HCV TPS Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status 06 – Redundant: degraded from fully redundant state. Degraded 07 – Redundant: Transition from non-redundant state.
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Intel® Server Board S5520HC / S5500HCV TPS Full Sensor Name (Sensor name in SDR) System Event (System Event) BB +1.1V IOH (BB +1.1V IOH) BB +1.1V P1 Vccp (BB +1.1V P1 Vccp) BB +1.1V P2 Vccp (BB +1.1V P2 Vccp) BB +1.5V P1 DDR3 (BB +1.5V P1 DDR3) BB +1.5V P2 DDR3 (BB +1.5V P2 DDR3) BB +1.8V AUX (BB +1.8V AUX) BB +3.3V (BB +3.3V) BB +3.3V STBY (BB +3.
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) BB +3.3V Vbat (BB +3.3V Vbat) BB +5.0V (BB +5.0V) BB +5.0V STBY (BB +5.0V STBY) BB +12.0V (BB +12.0V) BB -12.0V (BB -12.
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Intel® Server Board S5520HC / S5500HCV TPS Full Sensor Name (Sensor name in SDR) Sensor # Fan Tachometer Sensors (Chassis specific sensor names) Fan Present Sensors (Fan x Present) Fan Redundancy 1 (Fan Redundancy) Platform Applicability Sensor Type Appendix C: BMC Sensor Tables Event / Reading Type Event Offset Triggers 30h–39h Chassisspecific Fan Threshold 04h 01h 40h–45h Chassisspecific Fan 04h Generic 08h 01 - Device inserted 46h Chassisspecific Fan Generic 04h 0Bh Contrib.
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Power Supply 1 Status (PS1 Status) Power Supply 2 Status (PS2 Status) Power Supply 1 AC Power Input (PS1 Power In) Sensor # 50h 51h 52h Platform Applicability Chassisspecific Chassisspecific Chassisspecific Intel® Server Board S5520HC / S5500HCV TPS Sensor Type Power Supply 08h Power Supply 08h Event / Reading Type Event Offset Triggers Contrib. To System Status 05 - Nonredundant: insufficient resources.
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Intel® Server Board S5520HC / S5500HCV TPS Full Sensor Name (Sensor name in SDR) Power Supply 2 AC Power Input Sensor # 53h (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output 54h (PS1 Curr Out %) Power Supply 2 +12V % of Maximum Current Output 55h (PS2 Curr Out %) Power Supply 1 Temperature 56h (PS1 Temperature) Power Supply 2 Temperature 57h (PS2 Temperature) Processor 1 Status (P1 Status) Processor 2 Status (P2 Status) Processor 1 Thermal Margin 60h 61h Platform Applicability (
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 1 Thermal Control % Sensor # Platform Applicability 64h All 65h Dual processor only 66h All (P1 Therm Ctrl %) Processor 2 Thermal Control % (P2 Therm Ctrl %) Processor 1 VRD Temp (P1 VRD Hot) Processor 2 VRD Temp (P2 VRD Hot) Catastrophic Error (CATERR) CPU Missing (CPU Missing) IOH Thermal Trip (IOH Thermal Trip) 67h 68h 69h 6Ah Dual processor only All All All Intel® Server Board S5520HC / S5500HCV TPS Sensor T
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Intel® Server Board S5520HC / S5500HCV TPS Appendix D: Platform Specific BMC Appendix Appendix D: Platform Specific BMC Appendix Table 82.
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Appendix D: Platform Specific BMC Appendix Y: Support N: Not Support Power Unit Redundancy Support (PMBus-compliant Power Supply Support) ® Intel® Server Board S5520HC / S5500HCV TPS Intel Server Chassis SC5650DP Intel® Server Chassis SC5650BRP Intel® Server Chassis SC5600Base Intel® Server Chassis SC5600BRP Intel® Server Chassis SC5600LX N Y N Y Y Revision 1.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix E: POST Code Diagnostic LED Decoder Appendix E: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix E: POST Code Diagnostic LED Decoder  Intel® Server Board S5520HC / S5500HCV TPS Upper nibble bits = 1110b = Eh; Lower nibble bits = 1101b = Dh; the two are concatenated as EDh. Find the meaning of POST Code EDh in below table – Memory Population Error: RDIMMs and UDIMMs cannot be mixed in the system. Table 84.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix E: POST Code Diagnostic LED Decoder Progress Code Progress Code Definition USB 0x58 Resetting USB bus 0x59 Reserved for USB devices ATA / ATAPI / SATA 0x5A Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS 0x5C Resetting SMBUS 0x5D Reserved for SMBUS Local Console 0x70 Resetting the video controller (VGA) 0x71 Disabling the video controller (VGA) 0x72 Enabling the video controller (VGA) Remote Console 0x78 Resetting the c
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Appendix E: POST Code Diagnostic LED Decoder Progress Code 0xB8 Progress Code Definition Resetting the removable media device 0xB9 Disabling the removable media device Intel® Server Board S5520HC / S5500HCV TPS 0xBA Detecting the presence of a removable media device (CDROM detection, etc.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix F: POST Error Messages and Handling Appendix F: POST Error Messages and Handling Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Appendix F: POST Error Messages and Handling Intel® Server Board S5520HC / S5500HCV TPS Table 85. POST Error Messages and Handling Error Code Error Message Response 0012 CMOS date / time not set Pause 0048 Password check failed Pause 0108 Keyboard component encountered a locked error. No Pause 0109 Keyboard component encountered a stuck key error. No Pause 0113 Fixed Media The SAS RAID firmware can not run properly. The user should attempt to reflash the firmware.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix F: POST Error Messages and Handling Error Code Error Message Response 8542 DIMM_B1 Disabled. Pause 8543 DIMM_B2 Disabled. Pause 8544 DIMM_C1 Disabled. Pause 8545 DIMM_C2 Disabled. Pause 8546 DIMM_D1 Disabled. Pause 8547 DIMM_D2 Disabled. Pause 8548 DIMM_E1 Disabled. Pause 8549 DIMM_E2 Disabled. Pause 854A DIMM_F1 Disabled. Pause 854B DIMM_F2 Disabled.
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Appendix F: POST Error Messages and Handling Intel® Server Board S5520HC / S5500HCV TPS Error Code Error Message Response 92A3 Serial port component was not detected Pause 92A9 Serial port component encountered a resource conflict error Pause 92C6 Serial Port controller error No Pause 92C7 Serial Port component encountered an input error. No Pause 92C8 Serial Port component encountered an output error. No Pause 94C6 LPC component encountered a controller error.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix F: POST Error Messages and Handling POST Error Beep Codes The following table lists the POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users of error conditions. The beep code is followed by a user-visible code on the POST Progress LED’s. Table 86.
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Appendix G: Installation Guidelines Intel® Server Board S5520HC / S5500HCV TPS Appendix G: Installation Guidelines 1.
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Intel® Server Board S5520HC / S5500HCV TPS Appendix G: Installation Guidelines ® Description In an Intel Server Board S5520HC or S5500HCV based system with EFI shell as first boot device, after users press hot keys to enter RAID adapter configuration screen that hooks option ROM on INT 19h, the system may boot in to EFI shell instead. Guideline Type ‘exit’ and execute under the EFI shell, the RAID adapter configuration screen will show up if configuration screen hot keys were pressed during POST. 6.
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Glossary Intel® Server Board S5520HC / S5500HCV TPS Glossary Term Definition ACPI Advanced Configuration and Power Interface AHCI Advanced Host Controller Interface AMT Active Management Technology AP Application Processor APIC Advanced Programmable Interrupt Control ARP Address Resolution Protocol ASIC Application Specific Integrated Circuit ATS Address Translation Technology BBS BIOS Boot Specification BEV Boot Entry Vector BIOS Basic Input / Output System BIST Built-in Self Tes
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Intel® Server Board S5520HC / S5500HCV TPS Term Glossary Definition GPA Guest Physical Address GPIO General Purpose I/O HPA Host Physical Address HSC Hot-Swap Controller HT Hyper-Threading Hz Hertz (1 cycle / second) I2C Inter-Integrated Circuit Bus IA Intel® Architecture ICH I/O Controller Hub ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IOH I/O HUB IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface
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Glossary Term Intel® Server Board S5520HC / S5500HCV TPS Definition PCB Print Circuit Board PCI Peripheral Component Interconnect PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging PMBus Power Management Bus PMI Platform Management Interrupt POST Power-on Self Test PWM Pulse-Width Modulation QPI QuickPath Interconnect RAID Redundant Array of Independent Disks RAS Reliability, Availability, and Serviceability RASUM Reliability, Avai
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Intel® Server Board S5520HC / S5500HCV TPS Term Glossary Definition VID Voltage Identification VLSI Very-large-scale integration VRD Voltage Regulator Down VT Virtualization Technology VT-d Virtualization Technology for Directed I/O Word 16-bit quantity WS-MAN Web Service for Management XD bit Execute Disable Bit Revision 1.
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Reference Documents Intel® Server Board S5520HC / S5500HCV TPS Reference Documents See the following documents for additional information:  Intel® Server Boards S5520HC and S5500HCV Specification Update Revision 1.