SEL Troubleshooting Guide

Memory Subsystem System Event Log Troubleshooting Guide for Intel® S5500/S3420 Series Server Boards
50 Intel order number G74211-002 Revision 1.1
Byte
Field
Description
12
Sensor Number
13h
13
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 09h (digital Discrete)
14
Event Data 1
[7:6] – 10b = OEM code in Event Data 2
[5:4] – 00b = Unspecified Event Data 3
[3:0] – Event Trigger Offset as described in Table 57
15
Event Data 2
Not used
16
Event Data 3
Not used
Table 57: Sparing Configuration Status Sensor Event Trigger Offset – Next Steps
Event Trigger Offset
Description
Next Steps
Hex
Description
01h
The system has configured into
Spare Channel RAS mode.
Sparing mode is enabled in
setup.
Informational event only.
00h
The system has configured out of
Spare Channel RAS mode
Sparing mode is disabled,
either from setup or due to
error in which case post error
8500 also occurs.
1. If this event is accompanied by a post error 8500, there was a problem applying
the sparing configuration to the memory. Check for other errors related to the
memory and troubleshoot accordingly.
2. If there is no post error then sparing mode was simply disabled in BIOS setup
and this should be considered informational only.
7.1.4 Sparing Redundancy State Sensor
This sensor provides the RAS Redundancy state for the Spare Channel Mode.