SEL Troubleshooting Guide

Memory Subsystem System Event Log Troubleshooting Guide for Intel® S5500/S3420 Series Server Boards

56 Intel order number G74211-002 Revision 1.1

Byte

Field

Description

Event Data 1

[7:6] – 10b = OEM code in Event Data 2

[5:4] – 10b = OEM code in Event Data 3

[3:0] – Event Trigger Offset = 02h

Event Data 2

[7:5] – Reserved. Set to 0.

[4] – Channel Information Validity Check:

0b = Channel Number in Event Data 3 Bits[4:3] is not valid

1b = Channel Number in Event Data 3 Bits[4:3] is valid

[3] – DIMM Information Validity Check:

0b = DIMM Slot ID in Event Data 3 Bits[2:0] is not valid

1b = DIMM Slot ID in Event Data 3 Bits[2:0] is valid

[2:0] – Error Type:

000b = Parity Error Type not known

001b = Data Parity Error (not used)

010b = Address Parity Error

All other values are reserved.

Event Data 3

[7:5] – Indicates the Processor Socket to which the DDR3 DIMM having the ECC error is attached:

000b = Processor Socket 1

001b = Processor Socket 2

All other values are reserved.

[4:3] – Channel Number (if valid) on which the Parity Error occurred. This value will be indeterminate and

should be ignored if ED2 Bit [4] is 0b.

00b = Channel A or D (For Processor Socket 1, Processor Socket 2)

01b = Channel B or E

10b = Channel C or F

11b = Reserved

[2:0] – DIMM Slot ID (if valid) of the specific DIMM that was involved in the transaction that led to the

parity error. This value will be indeterminate and should be ignored if ED2 Bit [3] is 0b.

000b = DIMM Socket 1

001b = DIMM Socket 2

All other values are reserved.