Technical Product Specification

Power Sub-system Intel® Server System SC5650HCBRP TPS
Revision 1.2
Intel order number E81443-002
86
Table 49. Output Voltage Timing
Item Description Minimum Maximum Units
T
vout_rise
Output voltage rise time from each main output. 5.0* 70* msec
T
vout_on
All main outputs must be within regulation of each
other within this time.
50 msec
T
vout_off
All main outputs must leave regulation within this
time.
400 msec
* The 5VSB output voltage rise time shall be from 1.0 ms to 25.0 ms.
Figure 27. Output Voltage Timing
Table 50. Turn On / Off Timing
Item Description Loading Minimum Maximum Units
T
sb_on_delay
Delay from AC being applied to 5VSB being within
regulation.
1500
ms
T
ac_on_delay
Delay from AC being applied to all output voltages
being within regulation.
2500
ms
T
vout_holdup
Time all output voltages stay within regulation after
loss of AC.
75%
21
ms
T
pwok_holdup
Delay from loss of AC to de-assertion of PWOK 75% 20 ms
T
pson_on_delay
Delay from PSON
#
active to output voltages within
regulation limits.
5 400
ms
T
pson_pwok
Delay from PSON
#
deactive to PWOK being de-
asserted.
50
ms
T
pwok_on
Delay from output voltages within regulation limits to
PWOK asserted at turn on.
100 500
ms
Vout
10%
Vout
T
vout rise
T
vout_on
T
vout_off
V1
V2
V3
V4