Technical Product Specification

Table of Contents Intel® Server System SC5650HCBRP TPS
Revision 1.2
Intel order number E81443-002
iv
Table of Contents
1. Introduction .......................................................................................................................... 1
1.1 Chapter Outline ........................................................................................................ 1
1.2 Server System Use Disclaimer ................................................................................ 1
2. Overview ............................................................................................................................... 3
2.1 Intel
®
Server System SC5650HCBRP Feature Set ................................................. 3
2.1.1 Intel
®
Server System SC5650HCBRP Layout ......................................................... 5
2.1.2 Mechanical Locks .................................................................................................... 9
2.1.3 System Color ........................................................................................................... 9
2.1.4 Rack and Cabinet Mouting Option ........................................................................... 9
2.1.5 Server Board Connector and Component Layout .................................................... 9
2.1.6 Server Board Mechanical Drawings ...................................................................... 11
2.1.7 Rear I/O Layout ..................................................................................................... 20
3. Functional Architecture ..................................................................................................... 21
3.1 Intel
®
5520 I/O Hub (IOH) ...................................................................................... 23
3.1.1 Intel
®
QuickPath Interconnect ................................................................................ 23
3.1.2 PCI Express* Ports ................................................................................................ 23
3.1.3 Enterprise South Bridge Interface (ESI) ................................................................ 24
3.1.4 Manageability Engine (ME) .................................................................................... 24
3.1.5 Controller Link (CL) ................................................................................................ 24
3.2 Processor Support ................................................................................................. 25
3.2.1 Processor Population Rules .................................................................................. 25
3.2.2 Mixed Processor Configurations. ........................................................................... 25
3.2.3 Intel
®
Hyper-Threading Technology (Intel
®
HT) ..................................................... 27
3.2.4 Enhanced Intel SpeedStep
®
Technology (EIST) ................................................... 27
3.2.5 Intel
®
Turbo Boost Technology .............................................................................. 27
3.2.6 Execute Disable Bit Feature .................................................................................. 27
3.2.7 Core Multi-Processing ........................................................................................... 28
3.2.8 Direct Cache Access (DCA) .................................................................................. 28
3.2.9 Unified Retention System Support ......................................................................... 28
3.3 Memory Subsystem ............................................................................................... 30
3.3.1 Memory Subsystem Nomenclature ........................................................................ 30
3.3.2 Supported Memory ................................................................................................ 31