Technical Product Specification

Intel® Server System SC5650HCBRP TPS Power Sub-system
Revision 1.2
Intel order number E81443-002
65
4.1.3.6 Voltage Regulation
The power supply output voltages stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise
specified in the Voltage Regulation Limits table. All outputs are measured with reference to the
GND. The +12V and +5VSB outputs are measured at the power distribution board output
harness connector.
Table 23. Voltage Regulation Limits
Parameter Tolerance MIN NOM MAX Units
+ 12V - 5% / +5% +11.40 +12.00 +12.60 Vrms
+ 5VSB - 5% / +5% +4.75 +5.00 +5.25 Vrms
4.1.3.7 Dynamic Loading
The output voltages remain within limits specified for the step loading and capacitive loading
presented in the following table. The load transient repetition rate was tested between 5 Hz and
5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere between the MIN load and MAX load
defined in the following table.
Table 24. Transient Load Requirements
Output Max Δ Step Load Size Max Load Slew Rate Test Capacitive Load
12 V 32.0 A 1 0.5 A/μs 2200 μF
+5 VSB 0.5 A 0.5 A/μs 20 μF
Note:
1. Step loads on each 12V output may happen simultaneously.
2. The +12V should be tested with 2200
μF evenly split between the three +12V rails.
4.1.3.8 Capacitive Loading
The power supply is stable and meets all requirements with the following capacitive loading
ranges. Minimum capacitive loading applies to static load only.
Table 25. Capacitive Loading Conditions
Output MIN MAX Units
+12V 2000 11,000 μF
+5VSB 1 350 μF