Technical Product Specification

Intel® Server System SC5650HCBRP TPS Power Sub-system
Revision 1.2
Intel order number E81443-002
75
System addressing
Address2/Address1/
Address0
0/0/0 0/0/1 0/1/0 0/1/1 1/0/0 1/0/1 1/1/0 1/1/1
PMBus device read
addresses 2
B0h/B1h1 B2h/B3h B4h/B5h B6h/B7h B8h/B9h BAh/BBh BCh/BDh BEh/BFh
1
Non-redundant power supplies use the 0/0/0 address location
2
The addressing method uses the 7 MSB bits to set the address and the LSB to define whether
a device is reading or writing. The addresses defined above use 8 bits including the read/write
bit.
IPMI FRU Addressing:
If the power supply has a FRU (field replaceable unit) serial EEPROM; it should be located at
the following addresses.
System addressing
Address2/Address1/
Address0
0/0/0 0/0/1 0/1/0 0/1/1 1/0/0 1/0/1 1/1/0 1/1/1
FRU device addresses 2 A0h/A1h 1 A2h/A3h A4hA5h A6h/A7h A8h/A9h AAh/ABh ACh/ADh AEh/AFh
1
Non-redundant power supplies use the 0/0/0 address location.
2
The addressing method uses the 7 MSB bits to set the address and the LSB to define whether
a device is reading or writing. The addresses defined above use 8 bits including the read/write
bit.