Report

Errata and Contingencies S5000PSLROMBR
14 July 22, 2008
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 Errata 566
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Assertion 7A5587BC-5646-4DC4-9A5D-22F85AB2204E: FAILED.
PCI Express ports and bridges must implement Subsystem ID and
Subsystem Vendor ID Capability. This requirement not in effect
until 2009
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 Errata 1114
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Bit range 9:4 (Negotiated Link Width)in the Link Status register
(offset 12h) in the PCI Express Capability table is 0h. It must be
in the set of values {0x1, 0x2, 0x4, 0x8, 0xc, 0x10, 0x20}.
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 Errata 474
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
According to the PCI Express Base Specification, Rev 2.0 Section
7.8.8, this bit field is undefined when the link is not up. If there is
not PCIe device behind the bridge, then the link can NOT be up
and therefore the field is undefined. Bit 13 in the same register
(Link Status) can be used to determine if the link is active (up).
The PCIHCT uses the Presence Detect State bit of the Slot Status
register to determine whether a child device is present. However,
the Presence Detect State bit only returns valid data if the Slot
Implemented bit is set (bit 8 of PCIe capabilities register). If the
PCIe root port or downstream port will never have a device behind
it, the Slot Implemented bit is cleared to 0. Per the spec, PDS will
always be 1 when the Slot Implemented bit is clear. Therefore PDS
can not be used to determine device presence when the SI bit is
clear.