Report

Errata and Contingencies S5000PSLROMBR
18 July 22, 2008
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
PCI Compliance - Bit range 31:2 (Message Address)in the Message Address
register (offset 4h) in the MSI Capability table must be read-writable.
RESOLUTION: The following PCI Compliance test assertion failure is
allowed DDC8A893-6F85-4D69-BC79-874BA52E0A02
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 x64 Errata 1080
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
PCI Compliance test causes the system to hang after testing Power
Management capability of the graphics devices. This occurs after
the device are put into various D-states and then recovered to D0
state. Cause: The AMD/ATI graphics devices require that the
VBIOS be re-posted after transition to various D-states and
recovery to D0 state which the PCIHCT doesn't do.
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 x64 Errata 566
Failing test name PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Assertion 7A5587BC-5646-4DC4-9A5D-22F85AB2204E: FAILED.
PCI Express ports and bridges must implement Subsystem ID and
Subsystem Vendor ID Capability. This requirement not in effect
until 2009
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 x64 Errata 1114
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Bit range 9:4 (Negotiated Link Width)in the Link Status register
(offset 12h) in the PCI Express Capability table is 0h. It must be
in the set of values {0x1, 0x2, 0x4, 0x8, 0xc, 0x10, 0x20}.