Report

Errata and Contingencies S5000PSLSASR
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
The Bit 5 (Surprise Down Error Severity) in the Uncorrectable Error
Severity register (offset Ch) in the Advanced Error Reporting
Capability table must be read-only and always return 1 if the Bit 5
(Surprise Down Error Mask) in the Uncorrectable Error Mask
Register in the Advanced Errror Reporting Capability table is not
implemented
Additional information
(for example, test system in a
multiple system configuration)
Failure type
(Contingency, Errata, Incident)
Operating system
(Windows XP, Windows 2000, etc.)
ID number
Windows Server 2008 x86 Errata 1080
PCI Hardware Compliance Test
Failing test name
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
PCI Compliance test causes the system to hang after testing Power
Management capability of the graphics devices. This occurs after
the device are put into various D-states and then recovered to D0
state. Cause: The AMD/ATI graphics devices require that the
VBIOS be re-posted after transition to various D-states and
recovery to D0 state which the PCIHCT doesn't do.
Additional information
(for example, test system in a
multiple system configuration)
Failure type
(Contingency, Errata, Incident)
Operating system
(Windows XP, Windows 2000, etc.)
ID number
Windows Server 2008 x86 Errata 1113
PCI Hardware Compliance Test
Failing test name
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Bit 5 (Retrain Link) in the Link Control register (offset 10h) in the
PCI Express Capability table must always return 0 on reads even
though it is read-write.
Additional information
(for example, test system in a
multiple system configuration)
Failure type
(Contingency, Errata, Incident)
Operating system
(Windows XP, Windows 2000, etc.)
ID number
Windows Server 2008 x86 Errata 1115
PCI Hardware Compliance Test
Failing test name
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
PCI Compliance - Bit 3 (Read Completion Boundary) in the Link
Control register (offset 10h) in the PCI Express Capability table
must be read-only and always return 0 for switch ports
14 April 8, 2008