Report

S5000PSLSASR Errata and Contingencies
Windows Server 2008 x64 Errata 331
PCI Hardware Compliance Test
Failing test name
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
PCI Compliance - Bit range 31:2 (Message Address)in the Message
Address register (offset 4h) in the MSI Capability table must be
read-writable. RESOLUTION: The following PCI Compliance test
assertion failure is allowed DDC8A893-6F85-4D69-BC79-
874BA52E0A02.
Additional information
(for example, test system in a
multiple system configuration)
Failure type
(Contingency, Errata, Incident)
Operating system
(Windows XP, Windows 2000, etc.)
ID number
Windows Server 2008 x64 Errata 566
PCI Hardware Compliance Test
Failing test name
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Assertion 7A5587BC-5646-4DC4-9A5D-22F85AB2204E: FAILED.
PCI Express ports and bridges must implement Subsystem ID and
Subsystem Vendor ID Capability. This requirement not in effect
unitl 2009
Additional information
(for example, test system in a
multiple system configuration)
Failure type
(Contingency, Errata, Incident)
Operating system
(Windows XP, Windows 2000, etc.)
ID number
Windows Server 2008 x64 Errata 474
PCI Hardware Compliance Test
Failing test name
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
According to the PCI Express Base Specification, Rev 2.0 Section
7.8.8, this bit field is undefined when the link is not up. If there is
not PCIe device behind the bridge, then the link can NOT be up
and therefore the field is undefined. Bit 13 in the same register
(Link Status) can be used to determine if the link is active (up).
The PCIHCT uses the Presence Detect State bit of the Slot Status
register to determine whether a child device is present. However,
the Presence Detect State bit only returns valid data if the Slot
Implemented bit is set (bit 8 of PCIe capabilities register). If the
PCIe root port or downstream port will never have a device behind
it, the Slot Implemented bit is cleared to 0. Per the spec, PDS will
always be 1 when the Slot Implemented bit is clear. Therefore PDS
can not be used to determine device presence when the SI bit is
clear.
Additional information
(for example, test system in a
multiple system configuration)
April 8, 2008 17