Report

Intel® Server System SR2520SAXSR 4BErrata and Contingencies
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 x64 Errata 1113
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
Bit 5 (Retrain Link) in the Link Control register (offset 10h) in the
PCI Express Capability table must always return 0 on reads even
though it is read-write.
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 x64 Errata 1114
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
According to the PCI Express Base Specification, Rev 2.0 Section
7.8.8, this bit field is undefined when the link is not up. If there is
not PCIe device behind the bridge, then the link can NOT be up
and therefore the field is undefined. Bit 13 in the same register
(Link Status) can be used to determine if the link is active (up).
The PCIHCT uses the Presence Detect State bit of the Slot Status
register to determine whether a child device is present. However,
the Presence Detect State bit only returns valid data if the Slot
Implemented bit is set (bit 8 of PCIe capabilities register). If the
PCIe root port or downstream port will never have a device behind
it, the Slot Implemented bit is cleared to 0. Per the spec, PDS will
always be 1 when the Slot Implemented bit is clear. Therefore PDS
can not be used to determine device presence when the SI bit is
clear.
Additional information
(for example, test system in a
multiple system configuration)
Operating system
(Windows XP, Windows 2000, etc.)
Failure type
(Contingency, Errata, Incident)
ID number
Windows Server 2008 x64 Errata 1115
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
PCI Compliance - Bit 3 (Read Completion Boundary) in the Link
Control register (offset 10h) in the PCI Express Capability table
must be read-only and always return 0 for switch ports.
RESOLUTION: The following PCI Compliance assertion failure is
allowed 9A275B03-1072-43D6-B034-3DD306D24324
Mar 9, 2008 19