Report

Intel® Server System SR2520SAFR 4BErrata and Contingencies
May 9, 2008 13
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is e xcessive or if
there is no text)
D0
tes and
covery to D0 state which the PCIHCT doesn't do.
PCI Compliance test causes the system to hang after testing Power
Management capability of the graphics devices. This occurs after
the device are put into various D-states and then recovered to
state. Cause: The AMD/ATI graphics devices require that the
VBIOS be re-posted after transition to various D-sta
re
Additional information
(for example, test system in a
multiple system configuration)
etc.)
gency, Errata, Incident)
ID number
Operating system
(Windows XP, Windows 2000,
Failure type
(Contin
Windows Server 2008 x86 566 Errata
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is e xcessive or if
d
Vendor ID Capability. This requirement not in effect
nitl 2009
there is no text)
Assertion 7A5587BC-5646-4DC4-9A5D-22F85AB2204E: FAILED.
PCI Express ports and bridges must implement Subsystem ID an
Subsystem
u
Additional information
(for example, test system in a
multiple system configuration)
etc.)
gency, Errata, Incident)
ID number
Operating system
(Windows XP, Windows 2000,
Failure type
(Contin
Windows Server 2008 x86 1114 Errata
Failing test name
PCI Hardware Compliance Test
Applicable error message
(Type N/A if the error message
or failing text is e xcessive or if
there is no text)
is
S
t be used to determine device presence when the SI bit is
clear.
Bit range 9:4 (Negotiated Link Width)in the Link Status register
(offset 12h) in the PCI Express Capability table is 0h.
According to the PCI Express Base Specification, Rev 2.0 Section
7.8.8, this bit field is undefined when the link is not up. If there
not PCIe device behind the bridge, then the link can NOT be up
and therefore the field is undefined. Bit 13 in the same register
(Link Status) can be used to determine if the link is active (up).
The PCIHCT uses the Presence Detect State bit of the Slot Status
register to determine whether a child device is present. However,
the Presence Detect State bit only returns valid data if the Slot
Implemented bit is set (bit 8 of PCIe capabilities register). If the
PCIe root port or downstream port will never have a device behind
it, the Slot Implemented bit is cleared to 0. Per the spec, PDS will
always be 1 when the Slot Implemented bit is clear. Therefore PD
can no