Report

Intel® Server System SR2520SAFR 4BErrata and Contingencies
May 9, 2008 19
Applicable error message
(Type N/A if the error message
or failing text is excessive or if
there is no text)
According to the PCI Express Base Specification, Rev 2.0 Section
7.8.8, this bit field is undefined when the link is not up. If there is
not PCIe device behind the bridge, then the link can NOT be up
and therefore the field is undefined. Bit 13 in the same register
(Link Status) can be used to determine if the link is active (up).
The PCIHCT uses the Presence Detect State bit of the Slot Status
register to determine whether a child device is present. However,
the Presence Detect State bit only returns valid data if the Slot
Implemented bit is set (bit 8 of PCIe capabilities register). If the
PCIe root port or downstream port will never have a device behind
it, the Slot Implemented bit is cleared to 0. Per the spec, PDS will
always be 1 when the Slot Implemented bit is clear. Therefore PDS
can not be used to determine device presence when the SI bit is
clear.
Additional information
(for example, test system in a
multiple system configuration)
Additional Information
No additional information entered in section 3 of the Intel® Server System SR2520SAFR Readme file
at time of WLP submission ID 1289848.