SEL Troubleshooting Guide

System Event Log Troubleshooting Guide for PCSD Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
Miscellaneous Events
Revision 1.2 Intel order number G90620-003 103
Event Trigger Offset
Description
Next Steps
Hex
Description
01h
Hard reset
responsive. The timer is disabled by default, and has to
be enabled manually. It then requires an IPMI-aware
utility in the operating system that will reset the timer
before it expires. If the timer does expire, the BMC can
take action if it is configured to do so (reset, power
down, power cycle, or generate a critical interrupt).
3. Make sure you have support for this in your OS (typically
using a third-party IPMI-aware utility such as ipmitool or
ipmiutil along with the OpenIPMI driver).
4. If this is the case, it is likely your OS has hung, and you need
to investigate OS event logs to determine what may have
caused this.
02h
Power down
03h
Power cycle
08h
Timer interrupt