SEL Troubleshooting Guide

System Event Log Troubleshooting Guide for PCSD Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
Processor Subsystem
Revision 1.2 Intel order number G90620-003 67
6.5 Processor ERR2 Timeout Sensor
The BMC supports an ERR2 Timeout Sensor (1 per CPU) that asserts if a CPU’s ERR2 signal has been asserted for longer than a
fixed time period (> 90 seconds). ERR[2] is a processor signal that indicates when the IIO (Integrated IO module in the processor)
has a fatal error which could not be communicated to the core to trigger SMI. ERR[2] events are fatal error conditions, where the
BIOS and OS will attempt to gracefully handle error, but may not always do so reliably. A continuously asserted ERR2 signal is an
indication that the BIOS cannot service the condition that caused the error. This is usually because that condition prevents the BIOS
from running.
When an ERR2 timeout occurs, the BMC asserts/deasserts the ERR2 Timeout Sensor, and logs a SEL event for that sensor. The
default behavior for BMC core firmware is to initiate a system reset upon detection of an ERR2 timeout. The BIOS setup utility
provides an option to disable or enable system reset by the BMC on detection of this condition.
Table 56: Processor ERR2 Timeout Sensor Typical Characteristics
Byte
Field
Description
11
Sensor Type
07h = Processor
12
Sensor Number
7Ch = Processor 1 ERR2 Timeout
7Dh = Processor 2 ERR2 Timeout
7Eh = Processor 3 ERR2 Timeout
7Fh = Processor 4 ERR2 Timeout
13
Event Direction and
Event Type
[7] Event direction
0b = Assertion Event
1b = Deassertion Event
[6:0] Event Type = 03h (“digital” discrete)
14
Event Data 1
[7:6] – 00b = Unspecified Event Data 2
[5:4] – 00b = Unspecified Event Data 3
[3:0] – Event Trigger Offset = 1h (State Asserted)
15
Event Data 2
Not used
16
Event Data 3
Not used