SEL Troubleshooting Guide

System Event Log Troubleshooting Guide for PCSD

Platforms Based on Intel

Xeon

Processor E5 4600/2600/2400/1600/1400 Product Families

Memory Subsystem

Revision 1.2 Intel order number G90620-003 75

Rank Sparing Mode protects memory data by reserving a “Spare Rank” on each channel that has memory installed on it. If a

Correctable Error Threshold event occurs, the data from the failing rank is copied to the Spare Rank on the same channel, and the

failing DIMM is disabled. Because the Sparing Domain is no longer redundant, a Sparing Redundancy State SEL Event is logged.

Table 62: Sparing Redundancy State Sensor Typical Characteristics

Byte

Field

Description

Generator ID

0033h = BIOS SMI Handler

Sensor Type

0ch = Memory

Sensor Number

11h

Event Direction and

Event Type

[7] Event direction

0b = Assertion Event

1b = Deassertion Event

[6:0] Event Type = 0Bh (Generic Discrete)

Event Data 1

[7:6] – 10b = OEM code in Event Data 2

[5:4] – 10b = OEM code in Event Data 3

[3:0] – Event Trigger Offset

0h = Fully Redundant

2h = Redundancy Degraded

Event Data 2

Location

[7:4] = Sparing Domain

0-3 = Channel A-D for Socket

[3:2] = Reserved

[1:0] = Rank on DIMM

0-3 = Rank Number