SEL Troubleshooting Guide

System Event Log Troubleshooting Guide for PCSD

Platforms Based on Intel

Xeon

Processor E5 4600/2600/2400/1600/1400 Product Families

Memory Subsystem

Revision 1.2 Intel order number G90620-003 79

Table 65: Address Parity Error Sensor Typical Characteristics

Byte

Field

Description

Generator ID

0033h = BIOS SMI Handler

Sensor Type

0ch = Memory

Sensor Number

13h

Event Direction and

Event Type

[7] Event direction

0b = Assertion Event

1b = Deassertion Event

[6:0] Event Type = 6Fh (Sensor Specific)

Event Data 1

[7:6] – 10b = OEM code in Event Data 2

[5:4] – 10b = OEM code in Event Data 3

[3:0] – Event Trigger Offset = 2h

Event Data 2

[7:5] – Reserved. Set to 0.

[4] – Channel Information Validity Check:

0b = Channel Number in Event Data 3 Bits[4:3] is not valid

1b = Channel Number in Event Data 3 Bits[4:3] is valid

[3] – DIMM Information Validity Check:

0b = DIMM Slot ID in Event Data 3 Bits[2:0] is not valid

1b = DIMM Slot ID in Event Data 3 Bits[2:0] is valid

[2:0] – Error Type:

000b = Parity Error Type not known

001b = Data Parity Error (not used)

010b = Address Parity Error

All other values are reserved.

Event Data 3

[7:5] – Indicates the Processor Socket to which the DDR3 DIMM having the ECC error is attached:

0-3 = CPU1-4

All other values are reserved.

[4:3] – Channel Number (if valid) on which the Parity Error occurred. This value will be indeterminate and should be ignored if ED2

Bit [4] is 0b.

0-3 = Channel A, B, C, D for CPU1

Channel E, F, G, H for CPU2