SEL Troubleshooting Guide

Memory Subsystem
System Event Log Troubleshooting Guide for PCSD Platforms Based on Intel
®
Xeon
®
Processor E5 4600/2600/2400/1600/1400 Product Families
80 Intel order number G90620-003 Revision 1.2
Byte
Field
Description
Channel J, K, L, M for CPU3
Channel N, P, R, T for CPU4
[2:0] – DIMM Slot ID (if valid) of the specific DIMM that was involved in the transaction that led to the parity error. This value will
be indeterminate and should be ignored if ED2 Bit [3] is 0b.
0-2 = DIMM 1-3 on Channel
All other values are reserved.
7.5.2.1 Memory Address Parity Error Sensor – Next Steps
These are bit errors that are detected in the memory addressing hardware. An Address Parity Error implies that the memory address
transmitted to the DIMM addressing circuitry has been compromised, and data read or written is compromised in turn. An Address
Parity Error is logged as such in SEL but in all other ways is treated the same as an Uncorrectable ECC Error.
While the error may be due to a failing DRAM chip on the DIMM, it can also be caused by incorrect seating or improper contact
between the socket and DIMM, or by the bent pins in the processor socket.
1. If needed, decode DIMM location from hex version of SEL.
2. Verify the DIMM is seated properly.
3. Examine gold fingers on edge of the DIMM to verify contacts are clean.
4. Inspect the processor socket this DIMM is connected to for bent pins, and if found, replace the board.
5. Consider replacing the DIMM as a preventative measure. For multiple occurrences, replace the DIMM.