Technical Product Specification

Table of Contents Intel® Server Boards S5520HC, S5500HCV, and S5520HCT TPS
Revision 1.9
Intel order number E39529-013
iv
Table of Contents
1. Introduction .......................................................................................................................... 1
1.1 Chapter Outline ........................................................................................................ 1
1.2 Server Board Use Disclaimer .................................................................................. 1
2. Overview ............................................................................................................................... 2
2.1 Intel
®
Server Boards S5520HC, S5500HCV and S5520HCT Feature Set .............. 2
* The PCI Express* Gen 1 slot (x8 Mechanically, x4 Electrically) is not available when the
SAS module slot is in use and vice versa. ................................................................................. 4
**The Trusted Platform Module is only availabe in S5520HCTServer Board Layout ................ 4
Server Board Layout .................................................................................................................. 5
2.1.1 Server Board Connector and Component Layout .................................................... 5
2.1.2 Server Board Mechanical Drawings ........................................................................ 8
2.1.3 Server Board Rear I/O Layout ............................................................................... 16
3. Functional Architecture ..................................................................................................... 17
3.1 Intel
®
5520 and 5500 I/O Hub (IOH) ...................................................................... 20
3.1.1 Intel
®
QuickPath Interconnect ................................................................................ 20
3.1.2 PCI Express* Ports ................................................................................................ 20
3.1.3 Enterprise South Bridge Interface (ESI) ................................................................ 21
3.1.4 Manageability Engine (ME) .................................................................................... 21
3.1.5 Controller Link (CL) ................................................................................................ 21
3.2 Processor Support ................................................................................................. 22
3.2.1 Processor Population Rules .................................................................................. 22
3.2.2 Mixed Processor Configurations. ........................................................................... 22
3.2.3 Intel
®
Hyper-Threading Technology (Intel
®
HT) ..................................................... 24
3.2.4 Enhanced Intel SpeedStep
®
Technology (EIST) ................................................... 24
3.2.5 Intel
®
Turbo Boost Technology .............................................................................. 24
3.2.6 Execute Disable Bit Feature .................................................................................. 24
3.2.7 Core Multi-Processing ........................................................................................... 25
3.2.8 Direct Cache Access (DCA) .................................................................................. 25
3.2.9 Unified Retention System Support ......................................................................... 25
3.3 Memory Subsystem ............................................................................................... 27
3.3.1 Memory Subsystem Nomenclature ........................................................................ 27
3.3.2 Supported Memory ................................................................................................ 29
3.3.3 Processor Cores, QPI Links and DDR3 Channels Frequency Configuration ........ 30
3.3.4 Publishing System Memory ................................................................................... 32
3.3.5 Memory Interleaving .............................................................................................. 32
3.3.6 Memory Test .......................................................................................................... 33
3.3.7 Memory Scrub Engine ........................................................................................... 33
3.3.8 Memory RAS ......................................................................................................... 33
3.3.9 Memory Population and Upgrade Rules ................................................................ 34