Technical Product Specification

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Intel® Server Board S5520UR and

S5520URT

Intel order number E44031-012

Revision 1.9

May, 2011

Enterprise Platforms and Services Division - Marketing

Summary of content (178 pages)

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Intel® Server Board S5520UR and S5520URT Technical Product Specification Intel order number E44031-012 Revision 1.
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Revision History Intel® Server Board S5520UR and S5520URT TPS Revision History Date March 2009 Revision Number 1.0 Modifications Initial Release. October 2009 1.1 Updated section 3.2 - Memory Subsystem. January 2010 1.2  Updated section 2.1 and added Security Feature for S5520URT.  Updated section 2.2.3 - NIC Connector.  Added section 3.9 Trusted Platform Module. March 2010 1.3      Arpil 2010 1.4  Updated section 2.2.1 - Server Board Connector and Component Layout.
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Intel® Server Board S5520UR and S5520URT Disclaimers Disclaimers ® Information in this document is provided in connection with Intel products. No license, express or implied, by ® estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server Board S5520UR and S5520URT TPS Table of Contents 1. Introduction ........................................................................................................................1 1.1 Chapter Outline ......................................................................................................1 1.2 Server Board Use Disclaimer .................................................................................1 2. Overview ....................................
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Intel® Server Board S5520UR and S5520URT TPS 3.6.4 3.7 Table of Contents Wake-up Control ..................................................................................................36 Video Support ......................................................................................................36 3.7.1 Video Modes ........................................................................................................36 3.7.2 Dual Video ......................................................
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Table of Contents Intel® Server Board S5520UR and S5520URT TPS 6.2 Power Connectors ................................................................................................92 6.3 System Management Headers .............................................................................93 6.3.1 ® ® Intel Remote Management Module 3 (Intel RMM3) Connector.......................... 93 6.3.2 LCP/IPMB Header .............................................................................................
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Intel® Server Board S5520UR and S5520URT TPS 7.2 Table of Contents Integrated BMC Force Update Procedure .......................................................... 116 7.3 BIOS Recovery Jumper......................................................................................117 ® 8. Intel Light-Guided Diagnostics ....................................................................................119 8.1 5-Volt Standby LED ............................................................................
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Table of Contents Intel® Server Board S5520UR and S5520URT TPS 10.3.3 Europe (CE Declaration of Conformity) .............................................................. 137 10.3.4 BSMI (Taiwan) ...................................................................................................137 10.3.5 KCC (Korea) ......................................................................................................137 Appendix A: Integration and Usage Tips .........................................
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Intel® Server Board S5520UR and S5520URT TPS List of Figures List of Figures Figure 1. Intel® Server Board S5520UR ......................................................................................4 ® Figure 2. Intel Server Board S5520UR, S5520URT Layout .......................................................5 ® Figure 3. Intel Server Board S5520UR, S5520URT – Hole and Component Positions (1 of 2).. 7 ® Figure 4. Intel Server Board S5520UR, S5520URT – Hole and Component Positions (2 of 2) ..
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List of Figures Intel® Server Board S5520UR and S5520URT TPS Figure 32. Setup Utility — Hard Disk Order Screen Display ......................................................85 Figure 33. Setup Utility — CDROM Order Screen Display ........................................................85 Figure 34. Setup Utility — Floppy Order Screen Display ...........................................................86 Figure 35. Setup Utility — Network Device Order Screen Display .........................................
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Intel® Server Board S5520UR and S5520URT TPS List of Tables List of Tables Table 1. Intel® Server Board S5520UR, S5520URT Feature Set ................................................2 Table 2. Major Board Components .............................................................................................6 Table 3. Mixed Processor Configurations..................................................................................16 Table 4. Memory Running Frequency vs. Processor SKU .......................
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List of Tables Intel® Server Board S5520UR and S5520URT TPS Table 32. Setup Utility — Delete Boot Option Fields .................................................................84 Table 33. Setup Utility — Hard Disk Order Fields .....................................................................85 Table 34. Setup Utility — CDROM Order Fields........................................................................86 Table 35. Setup Utility — Floppy Order Fields ............................................
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Intel® Server Board S5520UR and S5520URT TPS List of Tables Table 66. RiserType and PEWIDTH Mapping ......................................................................... 111 Table 67. Trace Lengths .........................................................................................................111 Table 68. Power Budget .........................................................................................................112 Table 69.
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List of Tables Intel® Server Board S5520UR and S5520URT TPS xiv Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S5520UR, S5520URT. In addition, design-level information for specific subsystems can be obtained by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem.
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Overview 2. Intel® Server Board S5520UR and S5520URT TPS Overview The Intel® Server Board S5520UR is a monolithic printed circuit board with features that are designed to support the rack server markets. 2.1 Intel® Server Board S5520UR, S5520URT Feature Set ® Table 1. Intel Server Board S5520UR, S5520URT Feature Set Feature Processors Description Support ® ®  One or two Intel Xeon Processor 5500 Series with a 4.8 GT/s, 5.86 GT/s, or 6.
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Intel® Server Board S5520UR and S5520URT TPS Feature Overview LAN Description ® ® Two 10/100/1000 ports provided by Intel 82575 PHYs with Intel I/O Acceleration Technology 2 support. Security** Trusted Platform Module Server Management On-board ServerEngines* LLC Pilot II Controller  Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant  Integrated Super I/O on LPC interface ® Support for Intel Server Management Software 3.
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Overview 2.2 Intel® Server Board S5520UR and S5520URT TPS Server Board Layout ® Figure 1. Intel Server Board S5520UR 4 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS 2.2.1 Overview Server Board Connector and Component Layout The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and a description is given in Table 2. ® Figure 2. Intel Server Board S5520UR, S5520URT Layout Revision 1.
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Overview Intel® Server Board S5520UR and S5520URT TPS Table 2.
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Intel® Server Board S5520UR and S5520URT TPS 2.2.2 Overview Intel® Server Board S5520UR, S5520URT Mechanical Drawings ® Figure 3. Intel Server Board S5520UR, S5520URT – Hole and Component Positions (1 of 2) Revision 1.
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Overview Intel® Server Board S5520UR and S5520URT TPS ® Figure 4. Intel Server Board S5520UR, S5520URT – Hole and Component Positions (2 of 2) 8 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS Overview ® Figure 5. Intel Server Board S5520UR, S5520URT – Primary Side Keepout Zone (1 of 3) Revision 1.
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Overview Intel® Server Board S5520UR and S5520URT TPS ® Figure 6. Intel Server Board S5520UR, S5520URT– Primary Side Keepout Zone (2 of 3) 10 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS Overview ® Figure 7. Intel Server Board S5520UR, S5520URT– Primary Side Keepout Zone (3 of 3) Revision 1.
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Overview Intel® Server Board S5520UR and S5520URT TPS ® Figure 8. Intel Server Board S5520UR, S5520URT– Second Side Keepout Zone 12 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS 2.2.3 Overview Server Board Rear I/O Layout The following figure shows the layout of the rear I/O components for the server board. A Serial Port A D Dual USB Port Connector B Video E NIC Port 1 (1 Gb) C Dual USB Port Connector F NIC Port 2 (1 Gb) ® Figure 9. Intel Server Board S5520UR, S5520URT Rear I/O Layout Revision 1.
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Functional Architecture 3. Intel® Server Board S5520UR and S5520URT TPS Functional Architecture The architecture and design of the Intel® Server Board S5520UR, S5520URT is based on the Intel® 5520 Chipset I/O Hub (IOH) and ICH10R chipset. The chipset is designed for systems based on the Intel® Xeon® processor in FC-LGA 1366 socket B package with Intel® QuickPath Interconnect (Intel® QPI).
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Intel® Server Board S5520UR and S5520URT TPS 3.1 Functional Architecture Intel® Xeon® Processor 3.1.1 Processor Support ® The Intel Server Boards S5520UR supports the following processors:  One or two Intel® Xeon® Processor 5500 Series with a 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 95 W.  One or two Intel® Xeon® Processor 5600 Series with a 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 130 W.
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS Table 3. Mixed Processor Configurations Error Processor family not identical Severity Fatal System Action The BIOS detects the error condition and responds as follows:  Logs the error into the system event log (SEL).  Alerts the Integrated BMC of the configuration error with an IPMI command.  Does not disable the processor.  Displays “0194: Processor family mismatch detected” message in the error manager.  Halts the system.
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Intel® Server Board S5520UR and S5520URT TPS 3.1.2 Functional Architecture Turbo Mode The Turbo Mode feature allows extreme edition processors to program thresholds for power/current which can increase platform performance by 10%. If the processor supports this feature, the BIOS setup provides an option to enable or disable this feature. The default is disabled. 3.1.3 Hyperthreading ® ® Most Intel Xeon processors support hyper threading.
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Functional Architecture 3.1.5 Intel® Server Board S5520UR and S5520URT TPS Unified Retention System Support The server board complies with Intel®’s Unified Retention System (URS) and the Unified Backplate Assembly. The server board ships with a made-up assembly of Independent Loading Mechanism (ILM) and Unified Backplate at each processor socket. The URS retention transfers load to the server board via the unified backplate assembly.
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Intel® Server Board S5520UR and S5520URT TPS 3.2 Functional Architecture Memory Subsystem 3.2.1 Intel® QuickPath Memory Controller The Intel® Xeon® Processor 5500 Series and Intel® Xeon® Processor 5600 Series have an integrated memory controller in its package. The Intel® QuickPath Memory Controller supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies. The memory controller supports both registered DIMMs (RDIMMs) and unbuffered DIMMs (UDIMMs).
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS Single- and Dual-Rank – x8 DRAM with 1 Gb or 2 Gb technology – DDR3 1333, DDR3 1066, and DDR3 800 ® The Intel Xeon® Processor 5600 Series on the Intel® Server Board S5520UR, S5520URT supports the following DIMM and DRAM technologies: o RDIMMs: – Single-, Dual-, and Quad-Rank – The Intel® Xeon® Processor 5600 Series support all Intel® Xeon® Processor 5500 Series memory configuration.
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Intel® Server Board S5520UR and S5520URT TPS Functional Architecture In addition, rules in the following tables (Tables 3 and 4 and 5) also determine the global common memory system frequency. Revision 1.
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS Table 4. Memory Running Frequency vs. Processor SKU DIMM Type DDR3 800 800 Processor Integrated Memory Controller (IMC) Max. Frequency (Hz) 800 DDR3 1066 800 DDR3 1333 800 1066 800 1066 1066 1333 800 1066 1333 Memory Running Frequency (Hz) = Fastest Common Frequency of Processor IMC and Memory ® ® Table 5. Memory Running Frequency vs.
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Intel® Server Board S5520UR and S5520URT TPS Memory Running Frequency (Y/N) DIMM Populated Per Channel DIMM Type Functional Architecture 800MHz 1066MHz 1333MHz Command/Addres s Rate Ranks Per DIMM SR: Single-Rank DR: Dual-Rank QR: Quad-Rank Description when two UDIMMs (Single- or Dual-Rank) are installed in the same channel. w or w/o ECC Note: 1. One clock cycle for the DRAM commands arrive at the DIMMs to execute. 2. Two clock cycles for the DRAM commands arrive at the DIMMs to execute.
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Functional Architecture Memory Running Frequency (Y/N) DIMM Populated Per Channel DIMM Type 1.35V w/ECC RDIMM DDR3L 1.35V w/ECC Intel® Server Board S5520UR and S5520URT TPS 800MHz 1066MHz 1333MHz Command/Addre ss Rate Ranks Per DIMM SR: Single-Rank DR: Dual-Rank QR: Quad-Rank installed memory: 800 MHz, 1066 MHz 2 Y N N 1N Mixing SR , DR , QR UDIMM 1.5V w or w/o ECC 1 Y Y Y 1N SR or DR UDIMM 1.5V w or w/o ECC 2 Y Y Y 2N Mixing SR , DR UDIMM 1.
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Intel® Server Board S5520UR and S5520URT TPS 3.2.3 Functional Architecture Publishing System Memory  The BIOS displays the Total Memory of the system during POST if Display Logo is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system.  The BIOS displays the Effective Memory of the system in the BIOS setup.
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Functional Architecture 3.2.4 Memory RAS 3.2.4.1 RAS Features Intel® Server Board S5520UR and S5520URT TPS The server board supports the following memory RAS features:  Channel Independent Mode  Channel Mirroring Mode ® ® ® ® The memory RAS offered by the Intel Xeon Processor 5500 Series and Intel Xeon Processor 5600 Series is done at channel level, i.e., during mirroring, channel B mirrors channel A. All DIMM matching requirements are on a slot to slot basis on adjacent channels.
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Intel® Server Board S5520UR and S5520URT TPS Functional Architecture Processor 5500 Series and Intel® Xeon® Processor 5600 Series alternates between both channels for read transactions. Write transactions are issued to both channels under normal circumstances. When the system is in the Channel Mirroring mode, channel C and channel F of socket 1 and socket 2 respectively are not used. Hence, the DIMMs populated on these channels are disabled and hence do not contribute to the available physical memory.
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Functional Architecture 3.2.4.3.2 Intel® Server Board S5520UR and S5520URT TPS Mirroring DIMM Population Rules Variance across Nodes ® ® ® ® Memory mirroring in The Intel Xeon Processor 5500 Series and Intel Xeon Processor 5600 Series-based platforms is channel mirroring. Mirroring is not done across sockets, so each socket may have a different memory configuration. Channel mirroring in socket 1 and socket 2 are mutually independent.
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Intel® Server Board S5520UR and S5520URT TPS 3.2.
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS  If both processor sockets are populated, the next upgrade from the Single Channel mode installs DIMM_D1. This configuration results in an optimal memory thermal spread, as well as Non-Uniform Memory Architecture (NUMA) aware interleaving. The BIOS selects the Independent Channel mode of operation.
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Intel® Server Board S5520UR and S5520URT TPS 3.3 Functional Architecture Intel® 5520 Chipset IOH The Intel® 5520 Chipset component is an I/O Hub (IOH.) The Intel® 5520 Chipset provides a connection point between various I/O components and Intel® processors via the Intel® QPI interface. The Intel® 5520 Chipset IOH is capable of interfacing with up to 36 PCI Express* lanes, which can be configured in various combinations of x4, x8, x16 and limited x2 and x1 devices.
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Functional Architecture 3.4.1 Intel® Server Board S5520UR and S5520URT TPS PCI Subsystem The primary I/O buses for the Intel® Server Board S5520UR, S5520URT are PCI, PCI Express* Gen1 and PCI Express* Gen2 with six independent PCI bus segments. PCI Express* Gen1 and Gen2 are dual-simplex point-to point serial differential low-voltage interconnects. A PCI Express* topology can contain a host bridge and several endpoints (I/O devices). The signaling bit rate is 2.
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Intel® Server Board S5520UR and S5520URT TPS 3.4.2 Functional Architecture Serial ATA Support The ICH10R has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and data transfer rates of up to 3.0 Gb/s. The six SATA ports on the server board are numbered SATA-0 through SATA-5. The SATA ports can be enabled or disabled and/or configured by accessing the BIOS setup utility during POST. 3.4.2.
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Functional Architecture  3.5 Intel® Server Board S5520UR and S5520URT TPS One internal low-profile 2x5 header (J1J1) is provided to support low-profile USB solid state drives. I/O Module ® The Intel Server Board S5520UR, S5520URT supports a variety of I/O Module options using 2 x4 PCI Express* Gen2 Mezzanine connectors on the rear of the server board. For more information on these modules, see the Intel® Server Board S5520UR, S5520URT I/O Module Hardware Specification.
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Intel® Server Board S5520UR and S5520URT TPS Functional Architecture  16 GPIO ports (shared with Integrated BMC)  LPC to SPI Bridge for system BIOS support  SMI and PME support  ACPI compliant  Wake-up control The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features:  USB 2.
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Functional Architecture 3.6.1 Intel® Server Board S5520UR and S5520URT TPS Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These interfaces are not shared with the host system. At any time, only one dedicated interface may be enabled for management traffic. The default active interface is the NIC 1 port. For these channels, support can be enabled for IPMI-over-LAN and DHCP.
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Intel® Server Board S5520UR and S5520URT TPS Functional Architecture Table 10. Video Modes 2D Mode Resolution 640x480 800x600 1024x768 1152x864 1280x1024 1440x900 1600x1200 3.7.
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Functional Architecture Dual Monitor Video 3.8 Intel® Server Board S5520UR and S5520URT TPS Shaded if on-board video is set to "Disabled" Enabled Disabled Network Interface Controller (NIC) Network interface support is provided from the on-board Intel® 82575EB NIC, which is a single, compact component with two fully integrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports.
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Intel® Server Board S5520UR and S5520URT TPS 3.9 Functional Architecture Trusted Platform Module (TPM) – Supported only on S5520URT 3.9.1 Overview Trusted Platform Module (TPM) is a hardware-based security device that addresses the growing concern on boot process integrity and offers better data protection. TPM protects the system start-up process by ensuring it is tamper-free before releasing system control to the operating system.
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS operator presence indication by verifying the setup Administrator password. A TPM administrative sequence invoked from the operating system proceeds as follows: 1. User makes a TPM administrative request through the operating system’s security software. 2. The operating system requests the BIOS to execute the TPM administrative command through TPM ACPI methods and then resets the system. 3.
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Intel® Server Board S5520UR and S5520URT TPS Main Advanced Security Functional Architecture Server Management Administrator Password Status User Password Status Set Administrator Password [1234aBcD] Set User Password [1234aBcD] Front Panel Lockout Enabled/Disabled TPM State TPM Administrative Control Boot Options Boot Manager No Operation/Turn On/Turn
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS Table 13. TSetup Utility – Security Configuration Screen Fields Setup Item TPM State* Options Enabled and Activated Enabled and Deactivated Disabled and Activated Disabled and Deactivated Help Text Comments Information only. Shows the current TPM device state. A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available.
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Intel® Server Board S5520UR and S5520URT TPS Functional Architecture hardware enhancements. Key hardware elements of this platform are: Processor: Extensions to the IA-32 architecture allow for the creation of multiple execution environments, or partitions. This allows for the coexistence of a standard (legacy) partition and protected partition, where software can run in isolation in the protected partition, free from being observed or compromised by other software running on the platform.
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Functional Architecture Intel® Server Board S5520UR and S5520URT TPS 2. After administrator password is setup, press F10 to save and exit BIOS setup. 3. System will automatically reboot, go to BIOS setup Menu page, Security Tab, set TPM Administrative Control as Turn ON, press F10 to save and exit BIOS setup. 44 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS Functional Architecture 4. Go to BIOS setup Menu, Security Tab, TPM State should be Enabled & Activated. 3.10 Intel® Virtualization Technology for Directed I/O (Intel® VT-d) The Intel® Virtualization Technology is designed to support multiple software environments sharing same hardware resources. Each software environment may consist of an OS and applications. The Intel® Virtualization Technology can be enabled or disabled in the BIOS setup.
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3BPlatform Management 4. Intel® Server Board S5520UR and S5520URT TPS Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot II. The on-board platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBus) architecture used on this server board. 46 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS 3BPlatform Management Figure 14. Server Management Bus (SMBus) Block Diagram Revision 1.
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3BPlatform Management 4.1 4.1.1 Intel® Server Board S5520UR and S5520URT TPS Feature Support IPMI 2.0 Features  Integrated Baseboard Management Controller (Integrated BMC).  IPMI Watchdog timer.  Messaging support, including command bridging and user/session support.  Chassis device functionality, including power/reset control and BIOS boot flags support.  Event receiver device: The Integrated BMC receives and processes events from other platform subsystems.
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Intel® Server Board S5520UR and S5520URT TPS 3BPlatform Management  Acoustic management: Support for multiple fan profiles.  Signal testing support: The Integrated Baseboard Management Controller (Integrated BMC) provides test commands for setting and getting platform signal states.  The Integrated Baseboard Management Controller (Integrated BMC) generates diagnostic beep codes for fault conditions.  System GUID storage and retrieval.
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3BPlatform Management 4.2.2.1 Intel® Server Board S5520UR and S5520URT TPS Keyboard and Mouse The keyboard and mouse are emulated by the Integrated BMC as USB human interface devices. 4.2.2.2 Video Video output from the KVM subsystem is equivalent to the video output on the local console. Video redirection is available after video is initialized by the system BIOS. 4.2.2.3 Availability Up to two remote KVM sessions are supported.
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Intel® Server Board S5520UR and S5520URT TPS 4.2.3.1 3BPlatform Management Availability The default inactivity timeout is 30 minutes, but may be changed through the embedded web server. Media redirection sessions persist across system reset, but not across an AC power loss. 4.2.4 Web Services for Management (WS-MAN) The Integrated BMC firmware supports the Web Services for Management (WS-MAN) specification. 4.2.
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3BPlatform Management 4.3.2 Intel® Server Board S5520UR and S5520URT TPS Management Engine Firmware Update The Management Engine (ME) Firmware (FW) provides a set of IPMI OEM commands for performing the FW update. An update utility running on the host uses IPMI bridging functionality to send these commands to the ME through the Integrated BMC over the Integrated BMC/IPMB link. On Intel® server platforms, the ME FW uses a single operational image with a recovery image.
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Intel® Server Board S5520UR and S5520URT TPS 5. BIOS Setup Utility 5.1 Logo/Diagnostic Screen 4BBIOS Setup Utility The Logo/Diagnostic Screen displays in one of two forms:   If Quiet Boot is enabled in the BIOS setup, a logo splash screen displays. By default, Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press to hide the logo and display the diagnostic screen.
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4BBIOS Setup Utility 5.3.1 Intel® Server Board S5520UR and S5520URT TPS Operation The BIOS Setup has the following features:  Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® workstation BIOS is only available in English.  Console Redirection - The BIOS Setup is functional via console redirection over various terminal emulation standards.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility Each Setup menu page contains a number of features. Each feature is associated with a value field except those used for informative purposes. Each value field contains configurable parameters. Depending on the security option selected and (in effect) by the password, a menu feature’s value may or may not change. If a value cannot be changed, its field is made inaccessible and appears grayed out. Table 15.
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4BBIOS Setup Utility Key Option Save and Exit Intel® Server Board S5520UR and S5520URT TPS Description Pressing causes the following message to display: Save configuration and reset? Yes No If “Yes” is highlighted and is pressed, all changes are saved and the Setup is exited. If “No” is highlighted and is pressed, or the key is pressed, the user is returned to where they were before was pressed without affecting any existing values. 5.3.1.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.1 4BBIOS Setup Utility Main Screen Unless an error occurred, the Main screen is the first screen displayed when the BIOS Setup is entered. If an error occurred, the Error Manager screen displays instead. Main Advanced Security Server Management Boot Options Boot Manager Logged in as Platform ID System BIOS Version S5500.86B.xx.yy.
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4BBIOS Setup Utility Setup Item Memory Intel® Server Board S5520UR and S5520URT TPS Options Help Text Size Quiet Boot Information only. Displays the total physical memory installed in the system in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs. Enabled Disabled [Enabled] – Display the logo screen during POST. [Disabled] – Display the diagnostic screen during POST. [Enabled] – Go to the Error Manager for critical POST errors.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.2 4BBIOS Setup Utility Advanced Screen The Advanced screen provides an access point to configure several options. On this screen, the user selects the option they want to configure. Configurations are performed on the selected screen and not directly on the Advanced screen. To access this screen from the Main screen, press the right arrow until the Advanced screen is selected.
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4BBIOS Setup Utility 5.3.2.2.1 Intel® Server Board S5520UR and S5520URT TPS Processor Screen The Processor screen allows the user to view the processor core frequency, system bus frequency, and to enable or disable several processor options. This screen also allows the user to view information about a specific processor. To access this screen from the Main screen, select Advanced > Processor.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility Table 18. Setup Utility — Processor Configuration Screen Fields Setup Item Processor ID Options Help Text Comments Information only. Processor CPUID. Processor Frequency Information only. Current frequency of the processor. Microcode Revision Information only. Revision of the loaded microcode. L1 Cache RAM Information only. Size of the Processor L1 Cache. L2 Cache RAM Information only. Size of the Processor L2 Cache.
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4BBIOS Setup Utility Setup Item ® Intel Virtualization Technology Intel® Server Board S5520UR and S5520URT TPS Options Enabled Disabled Help Text ® Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions. Note: A change to this option requires the system to be powered off and then back on before the setting takes effect.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.2.2 4BBIOS Setup Utility Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed. This screen also allows the user to open the Configure Memory RAS and Performance screen. To access this screen from the Main screen, select Advanced > Memory.
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4BBIOS Setup Utility Intel® Server Board S5520UR and S5520URT TPS Table 19. Setup Utility — Memory Configuration Screen Fields Setup Item Total Memory Options Help Text Effective Memory Comments Information only. The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB. Information only. The amount of memory available to the operating system in MB or GB.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility 5.3.2.2.2.1 Configure Memory RAS and Performance Screen The Configure Memory RAS and Performance screen allows the user to customize several memory configuration options, such as whether to use Memory Mirroring. To access this screen from the Main screen, select Advanced > Memory > Configure Memory RAS and Performance.
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4BBIOS Setup Utility 5.3.2.2.3 Intel® Server Board S5520UR and S5520URT TPS Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA/SAS controller when it is present on the baseboard, module card of an Intel system. To access this screen from the Main menu, select Advanced > Mass Storage.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility Table 21. Setup Utility — Mass Storage Controller Configuration Screen Fields Setup Item ® Intel Entry SAS RAID Module Options Enabled Disabled Help Text ® Enabled or Disable the Intel SAS Entry RAID Module Comments Unavailable if the SAS Module (AXX4SASMOD) is not present.
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4BBIOS Setup Utility 5.3.2.2.4 Intel® Server Board S5520UR and S5520URT TPS Serial Ports Screen The Serial Ports screen allows the user to configure the Serial A [COM 1] and Serial B [COM2] ports. To access this screen from the Main screen, select Advanced > Serial Port. Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Figure 21.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.2.5 4BBIOS Setup Utility USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration.
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4BBIOS Setup Utility Intel® Server Board S5520UR and S5520URT TPS Table 23. Setup Utility — USB Controller Configuration Screen Fields Setup Item Detected USB Devices Options Help Text Comments Information only. Shows the number of USB devices in the system. USB Controller Enabled Disabled [Enabled] - All onboard USB controllers are turned on and accessible by the OS. [Disabled] - All onboard USB controllers are turned off and inaccessible by the OS.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.2.6 4BBIOS Setup Utility PCI Screen The PCI Screen allows the user to configure the PCI add-in cards, onboard NIC controllers, and video options. To access this screen from the Main screen, select Advanced > PCI.
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4BBIOS Setup Utility Intel® Server Board S5520UR and S5520URT TPS Setup Item Onboard NIC2 ROM Options Enabled Disabled Help Text If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC2 cannot be used to boot or wake the system. Onboard NIC iSCSI ROM Enabled Disabled If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC1 and NIC2 cannot be used to boot or wake the system.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.2.7 4BBIOS Setup Utility System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal characteristics of the system. To access this screen from the Main screen, select Advanced > System Acoustic and Performance Configuration.
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4BBIOS Setup Utility Main Intel® Server Board S5520UR and S5520URT TPS Advanced Security Server Management Administrator Password Status User Password Status Set Administrator Password [1234aBcD] Set User Password [1234aBcD] Front Panel Lockout Enabled/Disabled Boot Options Boot Manager No Operation/Turn On/Turn Off/Clear Ownership TPM State TPM Admin
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Intel® Server Board S5520UR and S5520URT TPS Setup Item Front Panel Lockout Options Enabled Disabled TPM State Enabled and Activated Enabled and Deactivated Disabled and Activated Disabled and Deactivated TPM Administrative Control No Operation Turn On Turn Off Clear Ownership 5.3.2.4 4BBIOS Setup Utility Help Text If enabled, locks the power button and reset button on the system's front panel. If [Enabled] is selected, power and reset must be controlled via a system management interface.
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4BBIOS Setup Utility Main Advanced Intel® Server Board S5520UR and S5520URT TPS Security Server Management Boot Options Assert NMI on SERR Enabled/Disabled Assert NMI on PERR Enabled/Disabled Resume on AC Power Loss Stay Off/Last state/Reset Clear System Event Log Enabled/Disabled FRB-2 Enable Enabled/Disabled O/S Boot Watchdog Timer Enabled/Disabled O/S Boot Watchdog Timer Policy Power off/Reset O/S Boot Watchdog Timer Timeout 5 minutes/10 minutes/15 minutes/20 minutes ACPI 1.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility Table 27. Setup Utility — Server Management Configuration Screen Fields Setup Item Assert NMI on SERR Options Enabled Disabled Help Text On SERR, generate an NMI and log an error. Note: [Enabled] must be selected for the Assert NMI on PERR setup option to be visible. Assert NMI on PERR Enabled Disabled On PERR, generate an NMI and log an error. Note: This option is only active if the Assert NMI on SERR option is [Enabled] selected.
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4BBIOS Setup Utility 5.3.2.4.1 Intel® Server Board S5520UR and S5520URT TPS Console Redirection Screen The Console Redirection screen allows the user to enable or disable console redirection and configure the connection options for this feature. To access this screen from the Main screen, select Server Management > Console Redirection. Server Management Console Redirection Console Redirection Disabled/Serial Port A/Serial Port B Flow Control None/RTS/CTS Baud Rate 9.6k/19.2k/38.4k/57.6k/115.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility Table 28. Setup Utility — Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial Port A Serial Port B Help Text Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. [Serial Port B] - Configure serial port B for console redirection.
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4BBIOS Setup Utility 5.3.2.5 Intel® Server Board S5520UR and S5520URT TPS Server Management System Information Screen The Server Management System Information screen allows the user to view part numbers, serial numbers, and firmware revisions. To access this screen from the Main screen, select Server Management > System Information.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.6 4BBIOS Setup Utility Boot Options Screen The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the desired boot device. To access this screen from the Main screen, select Boot Options.
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4BBIOS Setup Utility Setup Item Intel® Server Board S5520UR and S5520URT TPS Options boot devices. Help Text option for this position. Comments Hard Disk Order Set the order of the legacy devices in this group. Displays when one or more hard disk drives are in the system. CDROM Order Set the order of the legacy devices in this group. Displays when one or more CD-ROM drives are in the system. Floppy Order Set the order of the legacy devices in this group.
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Intel® Server Board S5520UR and S5520URT TPS 4BBIOS Setup Utility If all types of bootable devices are installed in the system, the default boot order is: 1. 2. 3. 4. 5. 6. CD/DVD-ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV (Boot Entry Vector) Device EFI Shell and EFI Boot paths 5.3.2.6.1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order.
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4BBIOS Setup Utility 5.3.2.6.2 Intel® Server Board S5520UR and S5520URT TPS Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order. Note that while you can delete the Internal EFI Shell in this screen, it is restored to the Boot Order on the next reboot. You cannot permanently delete the Internal EFI Shell. To access this screen from the Main screen, select Boot Options > Delete Boot Options.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.6.3 4BBIOS Setup Utility Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks. To access this screen from the Main screen, select Boot Options > Hard Disk Order. Boot Options Hard Disk #1 < Available Hard Disks > Hard Disk #2 < Available Hard Disks > Figure 32. Setup Utility — Hard Disk Order Screen Display Table 33. Setup Utility — Hard Disk Order Fields 5.3.2.6.
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4BBIOS Setup Utility Intel® Server Board S5520UR and S5520URT TPS Table 34. Setup Utility — CDROM Order Fields Setup Item CDROM #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. CDROM #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position. 5.3.2.6.5 Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.6.6 4BBIOS Setup Utility Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices. To access this screen from the Main screen, select Boot Options > Network Device Order. Boot Options Network Device #1 Network Device #2 Figure 35. Setup Utility — Network Device Order Screen Display Table 36.
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4BBIOS Setup Utility Intel® Server Board S5520UR and S5520URT TPS Table 37. Setup Utility — BEV Device Order Fields 5.3.2.7 Setup Item BEV Device #1 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. BEV Device #2 Available Legacy devices for this Device group. Set system boot order by selecting the boot option for this position.
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Intel® Server Board S5520UR and S5520URT TPS 5.3.2.8 4BBIOS Setup Utility Error Manager Screen The Error Manager screen displays any errors encountered during POST. Error Manager ERROR CODE Exit SEVERITY INSTANCE Figure 38. Setup Utility — Error Manager Screen Display Table 39. Setup Utility — Error Manager Screen Fields Setup Item Displays System Errors 5.3.2.9 Comments Information only. Displays errors that occurred during the POST.
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4BBIOS Setup Utility Intel® Server Board S5520UR and S5520URT TPS Table 40. Setup Utility — Exit Screen Fields Setup Item Save Changes and Exit Help Text Exit the BIOS Setup utility after saving changes. The system reboots if required. The [F10] key can also be used. Comments User prompted for confirmation only if any of the setup fields were modified. Discard Changes and Exit Exit the BIOS Setup utility without saving changes. The [Esc] key can also be used.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs 6. Connector/Header Locations and Pin-outs 6.1 Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server board. It lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 41.
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Connector/Header Locations and Pin-outs 6.2 Intel® Server Board S5520UR and S5520URT TPS Power Connectors The main power supply connection uses an SSI-compliant 2x12 pin connector (J2K1). In addition, there are three additional power related connectors:  One SSI-compliant 2x4 pin power connector (J3K1), which provides 12 V power to the CPU Voltage Regulators and Memory.  One SSI-compliant 1x5 pin connector (J1K2), which provides I2C monitoring of the power supply.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs Table 44. Power Supply Signal Connector Pin-out (J1K2) 6.3 Pin 1 Signal SMB_CLK_FP_PWR_R Color Orange 2 SMB_DAT_FP_PWR_R Black 3 SMB_ALRT_3_ESB_R Red 4 3.3 V SENSE- Yellow 5 3.3 V SENSE+ Green System Management Headers 6.3.
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Connector/Header Locations and Pin-outs 6.3.2 Intel® Server Board S5520UR and S5520URT TPS LCP/IPMB Header Table 46. LPC/IPMB Header Pin-out (J1H1) 6.3.3 Pin 1 Signal Name SMB_IPMB_5VSB_DAT Description Integrated BMC IMB 5V standby data line 2 GND Ground 3 SMB_IPMB_5VSB_CLK Integrated BMC IMB 5V standby clock line 4 P5V_STBY +5 V standby power SGPIO Header Table 47. SGPIO Header Pin-out (J1G5) Pin 6.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs Note: Control panel features are also routed through the bridge board connector at location J4G1, as is implemented in Intel® Server Systems configured using a bridge board and a hotswap backplane. 6.4.1 Power Button The BIOS supports a front control panel power button. Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset.
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Connector/Header Locations and Pin-outs 96 Intel® Server Board S5520UR and S5520URT TPS Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs 6.4.5 Power LED The green power LED is active when the system DC power is on. The power LED is controlled by the BIOS. The power LED reflects a combination of the state of system (DC) power and the system ACPI state. The following table identifies the different states that can be assumed by the power LED. Table 49.
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Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS The following table maps the system state to the LED state. For a complete list of events and their associated System Status, refer to the Intel® Server System Integrated Baseboard Management Controller Core External Product Specification. Table 50. System Status LED Indicator States Color Green State Solid on Ok System Status System ready Description Green ~1 Hz blink Degraded System degraded: BIOS detected 1.
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Intel® Server Board S5520UR and S5520URT TPS Color Amber State Solid on System Status Fatal Connector/Header Locations and Pin-outs Description Fatal alarm – system has failed or shut down: BIOS Detected 1. DIMM failure when there is one DIMM present and no good 1 memory is present . 1 2. Run-time memory uncorrectable error in non-redundant mode . 3. CPU configuration error (for instance, processor stepping mismatch). Integrated BMC Detected 1. CPU IERR signal asserted. 2. CPU 1 is missing. 3.
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Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS Table 52.
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Intel® Server Board S5520UR and S5520URT TPS 6.
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Connector/Header Locations and Pin-outs 6.6.2 Intel® Server Board S5520UR and S5520URT TPS NIC Connectors The server board provides two stacked RJ-45/2xUSB connectors side-by-side on the back edge of the board (J6A1 and J6A2). The pin-out for NIC connectors are identical and are defined in the following table. Table 54. RJ-45 10/100/1000 NIC Connector Pin-out (J6A1, J6A2) Pin 6.6.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs 6.6.4 Intel® I/O Expansion Module Connector (J2B1, J3B1) The server board provides 2x internal 50-pin mezzanine style connector (J2B1, J3B1) to accommodate proprietary form factor Intel® I/O Expansion Modules, which expand the IO capabilities of the server board without sacrificing an add-in slot from the riser cards. There are multiple IO modules for use on this server board.
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Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS Table 57. External RJ-45 Serial A Port Pin-out (J9A2) 1 Pin Signal Name SPB_RTS Description RTS (request to send) 2 SPB_DTR DTR (Data terminal ready) 3 SPB_OUT_N TXD (Transmit data) 4 GND Ground 5 SPB_RI RI (Ring Indicate) 6 SPB_SIN_N RXD (receive data) 7 SPB_DSR _DCD Data Set Ready/Data Carrier Detect 8 SPB_CTS CTS (clear to send) Table 58. Internal 9-pin Serial B Header Pin-out (J1A1) 6.6.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs Table 60.
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Connector/Header Locations and Pin-outs 6.7 Intel® Server Board S5520UR and S5520URT TPS Riser Card Slot ® The server board has one riser slot, utilizing Intel Adaptive Slot Technology, which serves both full-height and half-height cards with PCI-X and/or PCI-Express* interface depending on chassis configuration. Note: The PCI-X interface is supported using 2U Butterfly PCI Express*/PCI-X active riser. The riser connector is a 280-pin PCI Express* connector from FCI-Berg (Vendor P/N: 10027747-11110TLF).
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Intel® Server Board S5520UR and S5520URT TPS Pin Side B 22 Connector/Header Locations and Pin-outs Pin Side A 22 Pin Side B 93 PCI Express* Signal TN[0] { PE6_Tn [3] } PCI Express* Signal GND Pin Side A 93 PCI Express* Signal N12V PCI Express* Signal 12V 23 PME# 12V 23 94 GND RP[0] { PE6_Rn [3] } 94 24 PERST# 5V 24 95 GND RN[0] { PE6_Rp [3] } 95 25 GND 5V 25 96 TP[7] { PE7_Tp [0] } GND 96 26 GND 5V 26 97 TN[7] { PE7_Tn [0] } GND 97 27 GND 5V 27 98 GND RP[7] { PE
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Connector/Header Locations and Pin-outs Pin Side B 67 68 69 PCI Express* Signal GND TP[6] { PE5_Tn [1] } TN[6] { PE5_Tp [1] } PCI Express* Signal RN[7] { PE5_Rp [0] } GND GND Intel® Server Board S5520UR and S5520URT TPS Pin Side A 67 68 69 Pin Side B 138 139 140 PCI Express* Signal REFCLK+ [7] REFCLK- [7] Riser Type [3] PCI Express* Signal REFCLK- [6] GND Riser Type [2] Table 63. Pin Type Description 6.7.1 Pin Types 3.3 V 3.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs Table 64.
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Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS Table 65.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs Table 66. RiserType and PEWIDTH Mapping IOH Strapping Riser/Server board PEWIDTH[5] PEWIDTH[4] PEWIDTH[3] PEWIDTH[2] PEWIDTH[1] PEWIDTH[0] (Server board) RiserType[3] RiserType[2] RiserType[1] (Server board) RiserType[0] PEWIDTH[5] is pulled high by the server board while PEWIDTH[1] is controlled by the I/O expansion module. 6.7.2.
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Connector/Header Locations and Pin-outs Intel® Server Board S5520UR and S5520URT TPS Table 68. Power Budget Power Rails 3.3V 17.7 Max Current Per Rail (A) 5V 5 12V 7.3 3.3VAUX 1 N12V 1 It’s important to note that the above “Board-Level” power budget does not take into account the limitations placed at the “System-Level” power budget. The above current numbers should only be understood as the maximum current limit that the design can handle.
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Intel® Server Board S5520UR and S5520URT TPS Connector/Header Locations and Pin-outs When the server board is integrated into an Intel® Server System with fixed hard drives, system fan monitoring is supported through a custom 26-pin connector with the pin-out defined in the following table. ® Table 70.
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Jumper Blocks 7. Intel® Server Board S5520UR and S5520URT TPS Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: ▼ Figure 40. Jumper Blocks (J1C3, J1D1, J1D2, J1E32) 114 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS Jumper Blocks Table 71. Server Board Jumpers (J1E7, J1E8, J1D4, and J1H2) Jumper Name J1E7: BIOS Default Pins 1-2 System Results These pins should have a jumper in place for normal system operation. (Default) 2-3 If these pins are jumpered with AC power plugged, the BIOS settings are cleared within 5 seconds. These pins should not be jumpered for normal operation.
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Jumper Blocks Intel® Server Board S5520UR and S5520URT TPS Note: Removing AC power before performing the Restoring BIOS Defaults operation will cause the system to automatically power up and immediately power down, after the procedure is followed and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and re-install the AC power cord. Power up the system and proceed to the BIOS Setup utility to reset the desired settings. 7.1.
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Intel® Server Board S5520UR and S5520URT TPS Jumper Blocks 6. Perform the Integrated BMC firmware update procedure as documented in the README.TXT file that is included in the given Integrated BMC firmware update package. After successful completion of the firmware update process, the firmware update utility may generate an error stating that the Integrated BMC is still in update mode. 7. Power down and remove the AC power cord. 8. Open the server chassis. 9.
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Jumper Blocks Intel® Server Board S5520UR and S5520URT TPS The BIOS POST screen appears displaying progress and the system automatically boots to the EFI shell. The Startup.nsh file executes, updating the BIOS. 5. Once successfully updated, power down the system and remove AC power. 6. Replace the BIOS Recovery Jumper (J1D4) to its default location on pins 1-2. 7. Reapply AC power and power on the system. *DO NOT* interrupt the BIOS POST during the first boot. 8.
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Intel® Server Board S5520UR and S5520URT TPS 8. Intel® Light-Guided Diagnostics Intel® Light-Guided Diagnostics The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level issues. This section shows where each LED is located on the server board and describes the function of each LED. 8.1 5-Volt Standby LED Several server management features of this server board require that a 5-V standby voltage be supplied from the power supply.
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Intel® Light-Guided Diagnostics 8.2 Intel® Server Board S5520UR and S5520URT TPS Fan Fault LEDs Fan fault LEDs are present for the six fans and are located near each CPU fan header. Figure 42. Fan Fault LED Locations 120 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS 8.3 Intel® Light-Guided Diagnostics System Status LED The server board provides a LED for the system status. The location of the LED is shown in the following figure. Figure 43. System Status LED Location The bi-color System Status LED operates as follows: Table 72. System Status LED Color Off Green/ Amber State N/A Alternating Blink Criticality Not ready Not ready Green Green Solid on Blink System OK Degraded Revision 1.9 Description AC power off.
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Intel® Light-Guided Diagnostics Color State Intel® Server Board S5520UR and S5520URT TPS Criticality       Description Redundancy loss such as power supply or fan. This does not apply to non-redundant subsystems. PCI Express* link errors CPU failure/disabled – if there are two processors and one of them fails. Fan alarm – Fan failure. Number of operational fans should be more than the minimum number needed to cool the system. Non-critical threshold crossed – Temperature and voltage.
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Intel® Server Board S5520UR and S5520URT TPS 8.4 Intel® Light-Guided Diagnostics DIMM Fault LEDs Each DIMM slot has a DIMM Fault LED near the DIMM slot. Figure 44. DIMM Fault LED Locations Revision 1.
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Intel® Light-Guided Diagnostics 8.5 Intel® Server Board S5520UR and S5520URT TPS Post Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server board in the rear I/O area of the server board by the serial A connector. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number.
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Intel® Server Board S5520UR and S5520URT TPS Design and Environmental Specifications 9. Design and Environmental Specifications 9.1 Intel® Server Board S5520UR, S5520URT Design Specifications The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 73.
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Design and Environmental Specifications Intel® Server Board S5520UR and S5520URT TPS Figure 46. Power Distribution Block Diagram 126 Intel order number E44031-012 Revision 1.
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Intel® Server Board S5520UR and S5520URT TPS 9.2.1 Design and Environmental Specifications Processor Power Support ® ® The server board supports the Thermal Design Power (TDP) guideline for Intel Xeon processors. The Flexible Motherboard Guidelines (FMB) has also been followed to help determine the suggested thermal and current design values for anticipating future processor needs.
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Design and Environmental Specifications Intel® Server Board S5520UR and S5520URT TPS The power supply is provided with a reliable protective earth ground. All secondary circuits are connected to protective earth ground. Resistance of the ground returns to chassis does not exceed 1.0 mΩ. This path may be used to carry DC current. 9.3.2 Standby Outputs The 5 VSB output is present when an AC input greater than the power supply turn-on voltage is applied. 9.3.
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Intel® Server Board S5520UR and S5520URT TPS Design and Environmental Specifications Table 77. Transient Load Requirements Output +3.3 V +5 V 12 V1 + 12 V2 + 12 V3 + 12 V4 +5 VSB  Step Load Size (See note 2) 5.0 A 6.0 A 28.0 A Load Slew Rate Test capacitive Load 0.25 A/µsec 0.25 A/µsec 0.25 A/µsec 250 µF 400 µF 1,2 2200 µF 0.5 A 0.25 A/µsec 20 µF Notes: 1. Step loads on each 12 V output may happen simultaneously. 2.
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Design and Environmental Specifications 9.3.8 Intel® Server Board S5520UR and S5520URT TPS Common Mode Noise The Common Mode noise on any output does not exceed 350 mV pk-pk over the frequency band of 10 Hz to 30 MHz.   9.3.9 The measurement is made across a 100Ω resistor between each of the DC outputs, including ground, at the DC power connector and chassis ground (power subsystem enclosure). The test setup uses a FET probe such as Tektronix* model P6046 or equivalent.
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Intel® Server Board S5520UR and S5520URT TPS Design and Environmental Specifications Table 80. Output Voltage Timing Item Tvout_rise Description Output voltage rise time from each main output. Tvout_on Tvout_off Minimum 1 5.0 Maximum 1 70 Units Msec All main outputs must be within regulation of each other within this time. 50 Msec All main outputs must leave regulation within this time. 700 Msec Note: The 5 VSB output voltage rise time should be from 1.0 ms to 25.0 ms Figure 47.
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Design and Environmental Specifications Item Intel® Server Board S5520UR and S5520URT TPS Description Minimum Maximum Tpwok_on Delay from output voltages within regulation limits to PWOK asserted at turn on. 100 500 Tpwok_off Delay from PWOK de-asserted to output voltages (3.3 V, 5 V, 12 V, -12 V) dropping out of regulation limits. 1 Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal.
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Intel® Server Board S5520UR and S5520URT TPS 9.3.12 Design and Environmental Specifications Protection Circuits Protection circuits inside the power supply cause only the power supply’s main outputs to shut down. If the power supply latches off due to a protection circuit tripping, an AC cycle OFF for 15 seconds and a PSON# cycle HIGH for 1 second is able to reset the power supply. 9.3.12.1 Over-current Protection (OCP) The power supply has current limits to prevent the +3.
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9BRegulatory and Certification Information Intel® Server Board S5520UR and S5520URT TPS 10. Regulatory and Certification Information 10.1 Product Regulation Requirements Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations.
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Intel® Server Board S5520UR and S5520URT TPS      9BRegulatory and Certification Information BSMI Certification (Taiwan) GOST – Listed on one System Certification (Russia) Belarus – Listed on one System Certification (Belarus) KCC Certification (Korea) Ecology Declaration (International) 10.
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9BRegulatory and Certification Information Intel® Server Board S5520UR and S5520URT TPS 10.3 Electromagnetic Compatibility Notices 10.3.1 FCC Verification Statement (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: 1. This device may not cause harmful interference 2. This device must accept any interference received, including interference that may cause undesired operation.
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Intel® Server Board S5520UR and S5520URT TPS 9BRegulatory and Certification Information “Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications. English translation of the notice above: This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,” ICES-003 of the Canadian Department of Communications. 10.3.
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Appendix A: Integration and Usage Tips Intel® Server Board S5520UR and S5520URT TPS Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.  This server board only supports The Intel® Xeon® Processor 5500 Series and Intel® Xeon® Processor 5600 Series with 130 W and less Thermal Design Power (TDP).
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Intel® Server Board S5520UR and S5520URT TPS Appendix B: Integrated BMC Sensor Tables Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information.
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Appendix B: Integrated BMC Sensor Tables  Intel® Server Board S5520UR and S5520URT TPS Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor.
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Intel® Server Board S5520UR and S5520URT TPS Appendix B: Integrated BMC Sensor Tables Table 84. Integrated BMC Core Sensors Sensor Name Sensor # Platform Applicability Sensor Type Event/Readin g Type Event Offset Triggers Contrib.
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Appendix B: Integrated BMC Sensor Tables Sensor Name Sensor # Platform Applicability Intel® Server Board S5520UR and S5520URT TPS Sensor Type Event/Readin g Type Event Offset Triggers Contrib.
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Intel® Server Board S5520UR and S5520URT TPS Sensor Name Sensor # Platform Applicability Sensor Type Appendix B: Integrated BMC Sensor Tables Event/Readin g Type Event Offset Triggers Contrib. To System Status Assert/De -assert Readable Event Data Rearm Standby Value/Off sets BB +1.5V P1 DDR3 BB +1.5V P2 DDR3 BB +1.8V AUX BB +3.3V BB +3.3V STBY BB Vbat BB +5.0V BB +5.0V STBY BB +12.0V BB -12.0V Revision 1.
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Appendix B: Integrated BMC Sensor Tables Sensor Name Sensor # Platform Applicability Intel® Server Board S5520UR and S5520URT TPS Sensor Type Event/Readin g Type Event Offset Triggers Contrib.
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Intel® Server Board S5520UR and S5520URT TPS Sensor Name Sensor # Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Readin g Type Event Offset Triggers Contrib. To System Status Assert/De -assert Readable Event Data Rearm Standby Value/Off sets PS1 Status PS2 Status PS1 Power In PS2 Power In Revision 1.
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Appendix B: Integrated BMC Sensor Tables Sensor Name Sensor # Platform Applicability Intel® Server Board S5520UR and S5520URT TPS Sensor Type Event/Readin g Type Event Offset Triggers Contrib.
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Intel® Server Board S5520UR and S5520URT TPS Sensor Name Sensor # Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Readin g Type Event Offset Triggers Contrib. To System Status Assert/De -assert Readable Event Data Rearm Standby Value/Off sets P2 VRD Temp CATERR CPU Missing IOH Thermal Trip Revision 1.
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Appendix C: Management Engine Generated SEL Event Messages Intel® Server Board S5520UR and S5520URT TPS Appendix C: Management Engine Generated SEL Event Messages This appendix lists the OEM System Event Log message format of events generated by the Management Engine (ME). This includes the definition of event data bytes 10-16 of the Management Engine generated SEL records. For System Event Log format information, see the Intelligent Platform Management Interface Specification, Version 2.0. Table 85.
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Intel® Server Board S5520UR and S5520URT TPS Appendix C: Management Engine Generated SEL Event Messages =5..255 – Reserved Byte 7 – Event Data 3 = Table 86. Node Manager Health Event Node Manager Health Event Request Byte 1 - EvMRev =04h (IPMI2.
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Appendix D: POST Code Diagnostic LED Decoder Intel® Server Board S5520UR and S5520URT TPS Appendix D: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Intel® Server Board S5520UR and S5520URT TPS Appendix D: POST Code Diagnostic LED Decoder Table 88.
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Appendix D: POST Code Diagnostic LED Decoder Intel® Server Board S5520UR and S5520URT TPS Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble Checkpoint Description LED 0x28h MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 X X O X O X X X Testing memory 0x50h X O X O X X X X PCI Bus Enumerating PCI busses 0x51h X O X O X X X O Allocating resources to PCI busses 0x52h X O X O X X O X Hot Plug PCI controller initialization 0x53h X O X O X X O O
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Intel® Server Board S5520UR and S5520URT TPS Checkpoint Appendix D: POST Code Diagnostic LED Decoder Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble LED 0xB3h Description MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 O X O O X X O O Enabling/configuring a fixed media device 0xB8h O X O O O X X X Removable Media Resetting removable media device 0xB9h O X O O O X X O Disabling removable media device 0xBAh O X O O O X O X Detecting presence of a remov
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Appendix D: POST Code Diagnostic LED Decoder Intel® Server Board S5520UR and S5520URT TPS Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble Checkpoint Description LED 0xF5h MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 O O O O X O X O Exiting Sleep state 0xF8h O O O O O X X X OS has requested EFI to close boot services (ExitBootServices ( ) Has been called) 0xF9h O O O O O X X O OS has switched to virtual address mode (SetVirtualAddressMap ( ) Has been called
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Intel® Server Board S5520UR and S5520URT TPS Appendix E: POST Code Errors Appendix E: POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
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Appendix E: POST Code Errors Error Code 8140 8141 8160 8161 8170 8171 8180 8181 8190 8198 8300 84F2 84F3 84F4 84FF 8500 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 852A 852B 852C 852D 852E 852F 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 854A 854B 854C 854D 854E 854F 8560 8561 8562 8563 8564 156 Intel® Server Board S5520UR and S5520URT TPS Error Message Processor 01 Failed FRB-3 Timer. Processor 02 Failed FRB-3 Timer.
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Intel® Server Board S5520UR and S5520URT TPS Error Code 8565 8566 8567 8568 8569 856A 856B 856C 856D 856E 856F 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 858A 858B 858C 858D 858E 858F 85A0 85A1 85A2 85A3 85A4 Revision 1.9 Appendix E: POST Code Errors Error Message DIMM_B2 Component encountered a Serial Presence Detection (SPD) fail error. DIMM_B3 Component encountered a Serial Presence Detection (SPD) fail error. DIMM_B4 Component encountered a Serial Presence Detection (SPD) fail error.
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Appendix E: POST Code Errors Error Code 85A5 85A6 85A7 85A8 85A9 85AA 85AB 85AC 85AD 85AE 85AF 8601 8602 8603 8604 9000 9223 9226 9243 9246 9266 9268 9269 9286 9287 9288 92A3 92A9 92C6 92C7 92C8 94C6 94C9 9506 95A6 95A7 95A8 9609 9641 9667 9687 96A7 96AB 96E7 0xA022 0xA027 0xA028 0xA421 0xA500 0xA501 0xA5A0 0xA5A1 0xA5A4 0xA6A0 158 Intel® Server Board S5520UR and S5520URT TPS Error Message DIMM_B2 Uncorrectable ECC error encountered. DIMM_B3 Uncorrectable ECC error encountered.
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Intel® Server Board S5520UR and S5520URT TPS Appendix E: POST Code Errors POST Error Beep Codes The following table lists the POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user-visible code on the POST Progress LEDs. For complete details, refer to the Intel® S5500/S5520 Server Board Family BIOS External Product Specification. Table 90.
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Appendix F: Supported Intel® Server Chassis Intel® Server Board S5520UR and S5520URT TPS Appendix F: Supported Intel® Server Chassis The Intel® Server Board S5520UR is supported in the following Intel® rack-mount server chassis: ®  Intel Server Chassis SR2600 URBRP  Intel® Server Chassis SR2600 URLX  Intel® Server Chassis SR2625 URBRP  Intel® Server Chassis SR2625 URLX  Intel® Server Chassis SR1600 UR  Intel Server Chassis SR1600 URSAS  Intel® Server Chassis SR1625 UR  Intel® Serve
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Intel® Server Board S5520UR and S5520URT TPS Glossary Glossary This appendix contains important terms used in this document. For ease of use, numeric entries are listed first (e.g., “82460GX”) followed by alpha entries (e.g., “AGP 4x”). Acronyms are followed by non-acronyms.
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Glossary Intel® Server Board S5520UR and S5520URT TPS Term Definition ® IA Intel Architecture IBF Input Buffer ICH I/O Controller Hub ICMB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt I/OAT I/O Acceleration Technology IOH I/O Hub IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In
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Intel® Server Board S5520UR and S5520URT TPS Glossary Term PLD Programmable Logic Device Definition PMI Platform Management Interrupt POST Power-On Self Test PSMI Power Supply Management Interface PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing RMII Reduced Media-Independent Interface ROM Read Only Memory RTC Real-Time Clock (Component
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Reference Documents Intel® Server Board S5520UR and S5520URT Reference Documents See the following documents for additional information: 164  Intel® S5500/S5520 Server Board Family BIOS External Product Specification  Intel® Server System Integrated Baseboard Management Controller Core External Product Specification  Intel® 5500/5520 Chipset I/O Controller Hub External Design Specification Intel order number E44031-012 Revision 1.