White Paper - Power Management in Intel Architecture Servers

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Power Management in

Intel® Architecture Servers

White Paper

Intel® Architecture Servers

During the last decade, Intel has added several new technologies that enable users to

improve the power efficiency of Intel® architecture based platforms. Because these

technologies have been introduced in different generations of microprocessors and

chipsets over several years, it may not be apparent how they work together and impact the

performance of higher-level applications. This paper explains each power-related technology

and how they interplay in an Intel architecture-based platform. We present data showing

how users can reduce the power consumed by a system when applications don’t need full

processing power and also how the system can deliver higher performance with a power

boost during periods of high loads. Understanding these silicon-level technologies will

enable application developers, IT managers, and system users to harness Intel architecture’s

full potential to deliver energy-efficient performance.

April 2009

Summary of content (12 pages)

PAGE 1
Power Management in Intel® Architecture Servers White Paper Intel® Architecture Servers During the last decade, Intel has added several new technologies that enable users to improve the power efficiency of Intel® architecture based platforms. Because these technologies have been introduced in different generations of microprocessors and chipsets over several years, it may not be apparent how they work together and impact the performance of higher-level applications.
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White Paper: Power Management in Intel® Architecture Servers Table of Contents Background ��3 Demand Based Switching (DBS) ��4 Introduction to DBS ��
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White Paper: Power Management in Intel® Architecture Servers Background A computer system requires electrical power to perform various activities, such as fetching data and application programs, executing instructions delivered by software, displaying output results, communicating with users through various interfaces, and interacting with other devices on the network.
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White Paper: Power Management in Intel® Architecture Servers Demand Based Switching (DBS) Internal Operation of DBS Processor performance states (P-states) are a predefined set of Introduction to DBS DBS is a power-management technology developed by Intel, in which the applied voltage and clock speed of a microprocessor are kept at the minimum necessary levels for optimal performance of required operations [1].
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White Paper: Power Management in Intel® Architecture Servers Turbo Boost cores are in idle mode as shown in Figure 3, or as long as the package is operating within its thermal limit. Turbo mode speeds up the CPU Introduction to Intel® Turbo Boost Technology to utilize available power headroom, as needed, to get an extra A processor with turbo mode capabilities can run at frequencies higher than the advertised frequency of the processor if the physical performance boost [3].
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White Paper: Power Management in Intel® Architecture Servers Turbo Mode No Turbo Core 1 Core 0 Frequency (F) Intel® Turbo Boost Technology Core 3 Core 1 Core 0 Core 2 OR Workload Lightly Theaded or < TDP Frequency (F) Core 3 Core 2 Core 1 Core 0 Frequency (F) Active cores running workloads < TDP Figure 4. Turbo mode uses the available headroom in processor package power limits.
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White Paper: Power Management in Intel® Architecture Servers Intel® Intelligent Power Node Manager In the second scenario a user can use a utility which displays the operating frequencies of the processors. The user can see the transition of the CPU to the P0 state, which will be more than the marked frequency of the processor, and can verify that all active cores are in turbo mode. In the above example, the user will see a frequency between 2.67–2.
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White Paper: Power Management in Intel® Architecture Servers Node Manager - How it Works CPU Change P/T state from OS BIOS (SCI Handler or ASL code) Change Power Comsumption Instrumented PSUs Console Manager Change number of P/T-states available Power Comsumption IPMI or WSMAN Policy Set Power Budget Node Manger BMC *bmc polling NM works as a Closed Control Loop System Figure 6. Node Manager control flow.
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White Paper: Power Management in Intel® Architecture Servers Working Together power policies that can be implemented through NM. One strategy is to run the servers at full power during the day when many server Interactions and Usage Models Several applications can benefit from the boosted frequency that is higher than the marked frequency of the CPU.
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White Paper: Power Management in Intel® Architecture Servers Experimental Data and Analysis We put an Intel® Xeon® processor 5500 series platform server to test by stressing the server CPU at different loads while manipulating different NM policies and turning turbo mode on or off. The data collected are shown in Figures 8 and 9.
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White Paper: Power Management in Intel® Architecture Servers Power consumption with turbo mode enabled 135 130 Powers Watts 125 120 115 X X 110 X 105 P0 P3 X P6 X 100 20 30 40 50 60 70 P8 80 CPU % Figure 9. Power variation with P-state change and CPU utilization, with turbo mode. Several conclusions can be drawn: • The highest performance state of a turbo mode-enabled system consumes less power overall (an average of 110 watts versus 120 watts without turbo mode enabled).
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Glossary Advanced Configuration and Power Interface (ACPI): ACPI is an open-standard specification for unified OS-centric device configuration and power management. It brings power management into OS control, as opposed to BIOS central systems. ASL is the ACPI Source Language used for specifying the desired device behavior. C-state: The processor C-state is the processor’s capability to go into various low power idle states (with varying wake-up latencies).