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Intel

Server Board Set

SE8500HW4

Technical Product Specification

Intel order number D22893-001

Revision 1.0

May, 2005

Enterprise Platforms and Services – Marketing

Summary of content (132 pages)

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® Intel Server Board Set SE8500HW4 Technical Product Specification Intel order number D22893-001 Revision 1.
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Revision History Intel® Server Board Set SE8500HW4 Revision History Date May 2005 Revision Number 1.0 Modifications Initial release. Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Intel® Server Board Set SE8500HW4 Product Overview Table of Contents 1. Product Overview................................................................................................................. 1 1.1 2. Board Set Features.................................................................................................. 2 Processor and Chipset ........................................................................................................ 5 2.1 Processors Supported .....................
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Product Overview 4.1 DDR2 DIMM Support ............................................................................................. 22 4.2 Installation Order ................................................................................................... 22 4.3 Memory Initialization .............................................................................................. 22 4.4 Data Correction and Scrubbing ............................................................................. 23 4.
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Intel® Server Board Set SE8500HW4 5.6 Intelligent Platform Management Buses (IPMB) .................................................... 38 5.6.2 Keyboard Controller Style (KCS)/Low Pin Count (LPC) Bus ................................. 38 5.6.3 Inter-Chassis Management Bus (ICMB) ................................................................ 38 5.6.4 Serial Over LAN (SOL) .......................................................................................... 39 5.6.
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Product Overview 9. Intel® Server Board Set SE8500HW4 8.2.1 Power-Up Sequence.............................................................................................. 58 8.2.2 Power-Down Sequence ......................................................................................... 59 8.3 Reset ..................................................................................................................... 60 8.4 Interrupts...............................................................
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Intel® Server Board Set SE8500HW4 Product Overview 10.7 System Management BIOS ................................................................................... 81 10.8 Security.................................................................................................................. 81 11. BIOS User Interface............................................................................................................ 83 11.1 Overview............................................................
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Product Overview Intel® Server Board Set SE8500HW4 List of Figures Figure 1. Intel® Server Board Set SE8500HW4, Populated......................................................... 2 Figure 2. Intel® Server Board Set SE8500HW4 Interconnect Diagram........................................ 3 Figure 3. 64-bit Intel® Xeon™ Processors MP ............................................................................ 5 Figure 4. Memory Board Outline Diagram ............................................................
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Intel® Server Board Set SE8500HW4 Product Overview List of Tables Table 1. Processor Feature Overview ......................................................................................... 5 Table 2. Processor Installation Order .......................................................................................... 7 Table 3. PCI Expansion Slot Features....................................................................................... 11 Table 4. PCI Interrupt Mapping............................
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Product Overview Intel® Server Board Set SE8500HW4 Table 33. Power Budget ............................................................................................................ 58 Table 34. Typical Power-Up Timings ......................................................................................... 59 Table 35. Typical Power-Down Timings .................................................................................... 60 Table 36. Reset Types..................................................
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Intel® Server Board Set SE8500HW4 Product Overview Table 68. View Memory Configure Details Menu..................................................................... 100 Table 69. Memory Board #n Menu .......................................................................................... 101 Table 70. DIMM Labels Menu................................................................................................... 102 Table 71. Devices Menu ..............................................................
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Product Overview Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 1. Product Overview Product Overview The Intel® Server Board Set SE8500HW4 is the fourth generation of four-way Intel® IA32 Server Boards. The board set uses the Intel® E8500 Chipset, and the next generation of memory and processor technologies.
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Product Overview Intel® Server Board Set SE8500HW4 This document describes the Mainboard and Memory Board components of the Intel® Server Board Set SE8500HW4. Figure 1. Intel® Server Board Set SE8500HW4, Populated 1.
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Intel® Server Board Set SE8500HW4 Product Overview Server management with either the Intel® Management Module Professional or Intel® Management Module Advanced ATI* Radeon* 7000 video controller, with 16MB SDRAM Broadcom* BCM5704 NetXtreme* Gigabit Ethernet controller: provides two ports on the rear of the Mainboard LSI Logic* 53C1030 Ultra320* SCSI Controller: provides two independent Ultra320 SCSI interfaces Optional ROMB support: provides two channels of RAID 0, 1, 5, 10 or 50 Optional cus
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Product Overview Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 Processor and Chipset 2. Processor and Chipset 2.1 Processors Supported The Intel® Server Board Set SE8500HW4 supports 64-bit Intel® Xeon™ Processors MP which are based on the Intel® NetBurst™ microarchitecture. Several architectural and microarchitectural enhancements have been added to this processor, including an increased L2 cache size and, for some models, an integrated L3 cache. Table 1 provides a feature set overview of the 64-bit Intel® Xeon™ Processors MP.
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Processor and Chipset Intel® Server Board Set SE8500HW4 The 64-bit Intel® Xeon™ Processors MP includes the following advanced features: Intel® Extended Memory 64 Technology (EM64T) for executing both 32-bit and 64-bit applications simultaneously Intel® Hyper-Threading (HT) technology providing two logical processors Intel® Demand-Based Switching (DBS) for power savings Execute-Disable Bit for hardware support of security features Quad-channel DDR2 400MHz memory support PCI Express for faste
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Intel® Server Board Set SE8500HW4 2.1.2 Processor and Chipset Installation Order Some processor signals do not have on-die termination and must be terminated at an end agent. The Intel® Server Board Set SE8500HW4 Mainboard was designed with two separate Front Side Buses (FSBs). For each bus with a processor installed, the first socket on that bus must be used to ensure proper signal termination. A processor must be installed in socket 1 before socket 2, and socket 3 before socket 4.
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Processor and Chipset 2.2 Intel® Server Board Set SE8500HW4 Intel® E8500 Chipset The Intel® E8500 Chipset is the highest performance, most scalable platform offering in the 64bit Intel® Xeon™ Processor MP family.
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Intel® Server Board Set SE8500HW4 Processor and Chipset Intel® IOP332 Storage I/O Processor 2.2.3 The Intel® IOP332 Storage I/O Processor contains a PCI Express-to-PCI-X bridge and performs bridging functions between the PCI Express interface of the NB and PCI-X devices.
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Processor and Chipset Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 3. I/O Subsystems 3.1 PCI Subsystem I/O Subsystems The PCI subsystem consists of eight slots, seven available to standard PCI adapters and one for the Intel® Server Board Set SE8500HW4-specific Intel® Fibre Channel Module. Table 3.
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I/O Subsystems Device Intel® Server Board Set SE8500HW4 APIC INTA# INTB# INTC# INTD# LSI Logic* 53C1030 Intel IOP332 Storage I/O Processor (A) PX1A_XINT0_N PX1A_XINT1_N - - Intel® Fibre Channel Module Intel IOP332 Storage I/O Processor (A) PX1A_XINT2_N PX1A_XINT3_N - - 3.1.2 PCI IDSEL Signal The IDSEL signal is used as a chip-select for devices during read and write transactions.
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Intel® Server Board Set SE8500HW4 3.1.3 I/O Subsystems Bus Arbitration Signals Request (REQ#) signals indicate to the bus arbiter that an agent/device desires use of the bus. The Grant (GNT#) signal indicates to the agent/device that access to the bus has been granted. Every master has its own REQ#, which must be tri-stated while RST# is asserted. These are point-to-point signals which are assigned to every bus master.
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I/O Subsystems 3.1.5 Intel® Server Board Set SE8500HW4 PCI Hot Plug* Support PCI Hot Plug* is the concept of removing a standard PCI adapter card from a system without stopping the software or powering down the system as a whole. In the Intel® Server Board Set SE8500HW4, PCI Slot 2 supports the PCI Hot-Plug Specification, Revision 1.1 and is configured so that the PXH isolates the slot from the PCI bus when no adapter is present.
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Intel® Server Board Set SE8500HW4 3.1.5.3 Hot Removal Example 3.1.5.3.1 Under Microsoft Windows Server 2003, Enterprise Edition: 1. 2. 3. 4. 5. 6. I/O Subsystems Open the cover of the system to access the adapters and status LEDs. Double-click “Unplug/Eject” in the taskbar to open the “Unplug or Eject Hardware” menu. Select the device to be removed and click “Stop”. Wait for the power LED to turn off. Dis-engage rocker, retention, and/or safety devices. Remove the adapter. 3.1.5.3.
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I/O Subsystems 3.2 Intel® Server Board Set SE8500HW4 Ultra320 SCSI Subsystem A single LSI Logic* 53C1030 controller provides the on-board Ultra320 SCSI interface. The controller resides on the PCI Bus Segment A (PX1A), off the Intel® IOP332 Storage I/O Processor. For optimal performance, the controller is configured as a 64-bit PCI-X 100MHz device. The LSI Logic 53C1030 supports two Ultra320 SCSI channels, both validated for LVDS operation.
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Intel® Server Board Set SE8500HW4 3.3 I/O Subsystems Intel® RAID On Motherboard (ROMB) The Intel® IOP332 Storage I/O Processor, in conjunction with the LSI Logic 53C1030, provides an optional RAID On Motherboard (ROMB) solution which supports RAID levels 0, 1, 5, 10, and 50. A 2MB flash component and a non-volatile SRAM store the code and hardware configuration information.
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I/O Subsystems 3.4 Intel® Server Board Set SE8500HW4 Gigabit Ethernet A single Broadcom* BCM5704C controller provides the on-board Gigabit Ethernet interface. This controller has two ports that can independently operate at 1000/100/10 Mbps and support failover and teaming for greater reliability and performance.
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Intel® Server Board Set SE8500HW4 3.8 I/O Subsystems Video A single ATI* Radeon* 7000 video controller provides the on-board video interface.
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I/O Subsystems Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 Intel® Server Board Set SE8500HW4 Memory Board Intel® Server Board Set SE8500HW4 Memory Board 4. One to four Intel® Server Board Set SE8500HW4 Memory Boards plug vertically into the Intel® Server Board Set SE8500HW4 Mainboard.
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Intel® Server Board Set SE8500HW4 Memory Board Intel® Server Board Set SE8500HW4 Figure 5. Memory Board Component Diagram 4.1 DDR2 DIMM Support DDR2 memory offers an effective doubling of the clock rate over DDR memory since data transfers happen on both the rising and falling edge of the clock (double pumped). Due to the lower clock frequency, and improved manufacturing technology, a significant power savings can be achieved, especially when the data bus is not active.
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Intel® Server Board Set SE8500HW4 4.4 Intel® Server Board Set SE8500HW4 Memory Board Data Correction and Scrubbing The XMB employs a Single Device Data Correction (x8 SDDC) algorithm for the memory subsystem that will recover from a component failure during read and write transactions. This corrects and logs a correctable memory error, and logs uncorrectable memory errors. A patrol scrub can be turned on in the system BIOS that scrubs roughly 64GB of memory behind each XMB every day.
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Intel® Server Board Set SE8500HW4 Memory Board 4.5.1 Intel® Server Board Set SE8500HW4 Button, Retention Latch and LEDs The following sections provide an overview of the hardware required to support memory hot plug. See Section 10.1 for more information about memory hot plug support on the Intel® Server Board Set SE8500HW4. 4.5.1.1 Attention Button This is a user accessible push button that initiates the proper shut down of the Memory Board during a memory hot plug event.
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Intel® Server Board Set SE8500HW4 4.5.1.3 Intel® Server Board Set SE8500HW4 Memory Board LEDs All LEDs are controlled by the BIOS through the Independent Memory Interface (IMI). Table 8 describes the LEDs on the Memory Board. Table 8.
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Intel® Server Board Set SE8500HW4 Memory Board 4.5.6 Intel® Server Board Set SE8500HW4 Power The Baseboard supplies 12V and 3.3V power to the Memory Board. The Memory Board has on board regulators to generate 1.8V, 1.5V and 0.9V. The XMB requires 1.5V and 1.8V, the DIMMs require 1.8V and DIMM termination requires 0.9V. The I2C devices use the 3.3Vstby from the Mainboard. 4.6 4.6.
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Intel® Server Board Set SE8500HW4 5. Server Management Server Management Intel server management consists of many embedded technologies that consist of a combination of board instrumentation, sensors, interconnects, server management controllers, firmware algorithms, and the system BIOS. The Intel Server Management (ISM) 8.x application provides a systems management application for monitoring server hardware and operating system performance and health.
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Network Activity LEDs Power LED Identify LED Drive Activity/Fault LED System Status LED Reset Button System Identify Button Power Button Intel® Server Board Set SE8500HW4 Front Panel SDI Switch Server Management FRU EEPROM Temp Sensor Front Panel Connectors BASEBOARD DIMM SPD (16) spkr Aux. IPMB Connector FRU EEPROM PROCESSOR SOCKETS(4) Hot-swap Backplane Header Thermal Trip CPU 'Core' Temp CPU OEM NV ICMB Transceiver Header Chip Set PCI PME CPU FRU Baseboard Temp 1 Logic 2.
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Intel® Server Board Set SE8500HW4 5.1 Server Management Sahalee Baseboard Management Controller (BMC) The Sahalee Baseboard Management Controller (BMC) contains a 32-bit RISC processor and associated peripherals used to monitor the system for critical events. The Sahalee BMC is designed to be the central server management controller in an enterprise server system and is common to several Intel® Architecture 32-bit-based and Intel Itanium™ Processor-based platform implementations.
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Server Management 5.1.1 Intel® Server Board Set SE8500HW4 Sensor Data Record SDR (SDR) Repository The BMC implements a logical Sensor Data Record (SDR) repository device, as specified in the Intelligent Platform Management Interface Specification, Version 2.0. The SDR repository is accessible via all communication transports, even while the system is powered off. 5.1.
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Intel® Server Board Set SE8500HW4 5.1.3 Server Management System Event Log (SEL) The BMC allocates 65,536 bytes of non-volatile space for storing system events. Each event record is padded with an additional four bytes of timestamp, resulting in 20 bytes of storage space per record. A total of 3,276 SEL records can be stored in the system.
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Server Management Events Intel® Server Board Set SE8500HW4 Newest BIOS available from support.intel.
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Intel® Server Board Set SE8500HW4 Server Management Fan settings are configurable via SDRs to allow for the specific cooling requirements needed by system integrators. A test command can also be issued to manually force the fan speed to a selected value, overriding any other control or policy. Ambient system temperature is determined from address 0x90 on private I2C bus 0, which for the Intel® Server Platform SR4850HW4 and Intel® Server Platform SR6850HW4 is a sensor on the SCSI Backplane Board.
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Server Management 5.3 Intel® Server Board Set SE8500HW4 ACPI Power Control The Intel® Server Board Set SE8500HW4 supports ACPI S0, S1 and S5 sleep states. When the system is operating in ACPI mode, the operating system retains control of the powering on of the system. During ACPI mode, operating system policy determines the entry methods and wakeup sources for each sleep state. An ACPI-enabled operating system generates a System Management Interrupt (SMI) to request that the system enables ACPI support.
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Intel® Server Board Set SE8500HW4 Server Management ACPI Sleep State S0 Power Switch Protected Reset Switch Protected S1 Partial1 Protected S5 Unprotected Unprotected 1. The system will wake from the power switch but holding the button for four seconds is blocked. 5.4 Fault Resilient Booting (FRB) When a system reset signal is recognized by the chipset, all processors execute initialization microcode and one is chosen as the bootstrap processor (BSP).
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Server Management 5.4.2 Intel® Server Board Set SE8500HW4 FRB2 The BIOS requests the BMC to start a second 10-minute timer to ensure the system completes the BIOS POST. The FRB2 timer is enabled before the FRB3 timer is disabled to prevent a gap in FRB coverage. The BIOS requests the BMC to disable the FRB2 timer before the option ROMs are scanned, the BIOS setup is entered, or prior to displaying a request for a boot password.
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Intel® Server Board Set SE8500HW4 Server Management that the FRB3 timer halt signal has become de-asserted after having previously been asserted by the BIOS to disable the FRB3 timer. 5.6 Remote Management and External Interfaces to the BMC Several external BMC interfaces are available to enable a variety of options for remote server management. Additional detail on most of these interfaces can be obtained from the IPMI 2.0 Specification.
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Server Management 5.6.1 Intel® Server Board Set SE8500HW4 Intelligent Platform Management Buses (IPMB) The IPMB is a communication protocol that utilizes a 100 KB/s I2C bus. The IPMB implementation in the BMC is compliant with the IPMB v1.0, revision 1.0, with the BMC having an IPMB slave address of 0x20. The BMC both sends and receives IPMB messages over the IPMB interface. Non-IPMB messages received via the IPMB interface are discarded.
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Intel® Server Board Set SE8500HW4 5.6.4 Server Management Serial Over LAN (SOL) Serial Over LAN (SOL) provides bi-directional transport of system COM2 serial data encapsulated in IPMI over LAN packets. This provides out-of-band LAN access to the BIOS console redirection, service partition application communication, or operating system console interaction without the BIOS or software being LAN-enabled or aware of anything beyond a serial port interface.
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Server Management 5.7 Intel® Server Board Set SE8500HW4 Event Filtering and Alerting The BMC implements the following IPMI 2.0 alerting features: Platform Event Filtering (PEF) Dial Page Alerting Alert over LAN Alert over Serial/PPP 5.7.1 Platform Event Filtering (PEF) The Platform Event Filtering (PEF) feature provides a configurable mechanism to allow SEL events to trigger alert actions.
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Intel® Server Board Set SE8500HW4 Event Filter # 10 Server Management Offset Mask Events Power Down, Power Cycle & Reset Watchdog Timer 11 OEM System Boot Event System Restart (Reboot) 12 - Reserved 5.7.2 Dial Page Alerting Dial page alerting operates using an external modem connected to the system’s onboard EMP serial connection on COM2. With dial paging, the system can be configured to automatically dial up a paging service when a platform event occurs.
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Server Management Intel® Server Board Set SE8500HW4 The following Alert over LAN resource sizes are platform-specific. Refer to the platform BMC EPS for their values. LAN Alert Destination Count Refer to IPMI 2.0 Specification for additional details on PET Alerts feature. 5.7.4 Alert over Serial/PPP Alert over Serial/PPP uses the same IP/UDP packet encapsulation as Alert over LAN, but allows alerts to be delivered via modem to a PPP enabled destination.
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Intel® Server Board Set SE8500HW4 6. Jumpers 6.1 Mainboard Password Clear Jumpers BIOS Write Protect Default BIOS Recovery Default Enabled 3 J4A1 A Default Enabled 3 J4A2 Circuit Breaker Type Default Enabled 3 NVRAM Clear Enabled 3 J4A3 J4A4 B Default 100 V 15 A 3 J4J3 CPU 3 CPU 4 CPU 2 CPU 1 TP01446 Figure 10. Mainboard Jumper Locations 43 Revision 1.
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Jumpers Intel® Server Board Set SE8500HW4 Table 16.
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Intel® Server Board Set SE8500HW4 Jumpers Servers connected to high-line power (200/208/220/230/240VAC) do not have a power consumption threshold.
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Jumpers Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 7. Connectors 7.1 SCSI Connectors The Intel® Server Board Set SE8500HW4 Mainboard has two unshielded 68-pin SCSI connectors for SCSI channel A and B. SOCKET 1 SOCKET 34 SOCKET 68 68 POSITION DEVICE CONNECTOR SOCKET 35 Figure 11. 68-Pin SCSI Connector Table 17.
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Connectors Intel® Server Board Set SE8500HW4 Pin 7.
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Intel® Server Board Set SE8500HW4 Pin 49 Signal Name CP_SPKR_OUT_N Connectors Signal Description Speaker signal to front panel 55 NIC1_LED NIC 1 activity LED signal 57 ID_LED ID LED Signal 60 CP_BTN_PWR_ON Control panel Power Button signal 63 SYS_STATUS_AMB_LED System Status amber LED signal 64 CD_PRES_N CD drive presence signal 67 CP_ID_BUTTON_RAW Control panel ID button signal 69 CP_BTN_NMI Control panel NMI button 71 NIC2_LED NIC2 activity LED signal 74 I2C_IPMB_SCL IPMB I2
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Connectors 7.4 Intel® Server Board Set SE8500HW4 USB The Intel® Server Board Set SE8500HW4 has one internal USB 2.0 header. Table 20. 4-pin Internal USB Header 7.5 Pin 1 Signal Fused Voltage Controlled Current (VCC) (+5 V with over-current monitoring) 2 USBP2N (differential data line) 3 USBP2P (differential data line) 4 GND (ground) SATA The Intel® Server Board Set SE8500HW4 has one Serial ATA (SATA) header. Table 21.
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Intel® Server Board Set SE8500HW4 7.6 Connectors Power The Intel® Server Board Set SE8500HW4 has three connectors for the power subsystem, two 12-pin connectors which provide primary power and one 2x15 header for power subsystem signals and 3.3Vstby. Table 22. 12-pin Power Connector Pinout Pins Signal 1-6 GND 7-12 +12V Table 23. 30-pin Power Signal Header Pinout Pins Signal Description 1,17,25,30 GND 6,7,10,12,14,15,24 3.
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Connectors 7.7 Intel® Server Board Set SE8500HW4 Rear Panel Connectors 7.7.1 Video ® The Intel Server Board Set SE8500HW4 has one standard 15-pin video connector. Table 24.
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Intel® Server Board Set SE8500HW4 Connectors Table 25. Stacked Ethernet Connector Pinout Pin Signal LED Signals 27 DNW_LINKB10_N Description Lower (LAN2) green status LED cathode signal indicating LAN2 activity 28 DNW1_ACT_N_R Lower (LAN2) green status LED anode to 100-ohm pullup to 3.
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Connectors Intel® Server Board Set SE8500HW4 The Intel® Server Board Set SE8500HW4 also provides an RJ45 connector that connects to the IMM Advanced for out-of-band server management features. This out-of-band connector is also referred to as the Generic Communication Module (GCM), or server management Ethernet controller. Table 26.
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Intel® Server Board Set SE8500HW4 7.7.4 Connectors USB ® The Intel Server Board Set SE8500HW4 has one stacked USB 2.0 connector. Table 28.
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Connectors 7.8.3 Intel® Server Board Set SE8500HW4 3-pin Chassis Intrusion Table 31. 3-pin Chassis Intrusion Pinout 7.8.4 Pin 1 Signal Intrusion event 2 GND 3 Intrusion button attached I2C POST Code Headers The Mainboard has a 5-pin header (with the fourth pin removed) for an I2C POST-code card. The I2C signals are from the SMB bus in the ICH5. The data and clock signals are pulled up to 3.3Vstby. Table 32.
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Intel® Server Board Set SE8500HW4 8. Electrical Specifications 8.1 Power Generartion Electrical Specifications Input power to the Mainboard is 12V and 3.3Vstby; all other required voltages are generated by Voltage Regulator Down (VRD) circuits and Voltage Regulator Modules (VRMs) on the Mainboard. The processor core voltages for processor sockets 1 and 2 are generated by VRDs and processors 3 and 4 get their core voltage from VRMs.
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Electrical Specifications Intel® Server Board Set SE8500HW4 Table 33. Power Budget Mainboard Subsystem Qty 1 +12V 147W Processors 4 448W Memory 16 192W PCI-X* slots 3 45W PCI Express* slots 4 80W Intel® Fibre Channel Module 1 15W ® Intel Server Board Set SE8500HW4 Total 8.2 927W +3.3Vstby 15W 15W Power Timing 8.2.1 Power-Up Sequence POWER_SW_L (I) t1 SM_PWRBTN_L (O) t2 SLP_S5P_L (I) t3 PS_ON_L (O) t4 SYS_PWROK (I) Figure 14. Typical Power-Up Sequence Revision 1.
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Intel® Server Board Set SE8500HW4 Electrical Specifications Table 34. Typical Power-Up Timings Ref t1 Description Time from front-panel power button push to BMC asserting the power button to the chipset. This includes the private store update for Pwr State change, which is on the order of 500ms + overhead, which accounts for other task completion time like Init Agent. BMC also debounces signal for 50ms.
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Electrical Specifications Intel® Server Board Set SE8500HW4 Table 35. Typical Power-Down Timings Ref t1 t2 t3 t4 8.3 Description Time from front-panel power button push, to BMC asserting the power button to the chipset. BMC debounces the power button input for 50ms Time from BMC asserting power button to chipset, until chipset responds with SLP_S5_L. Dependent on chipset setup. Time from when SLP_S5_L is asserted, to when BMC deasserts PS_ON_L to complete system power-off.
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Intel® Server Board Set SE8500HW4 Electrical Specifications Table 36. Reset Types Reset Type Description Front Panel Power Button De-asserts PS_ON_L to the power supply and causes the system to shut down. FP_RST_BTN_N ITP_RST These signals are connected to the “Sources of Reset” logic inside the PLD. Any time any one of these signals is transitions LOW, the output of the logic SYS_ICH_RST asserts the SYS_RST_N to ICH5. Upon which ICH5 asserts PCI_RST_N back to PLD.
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Electrical Specifications 8.5 Intel® Server Board Set SE8500HW4 Clocks The Intel® Server Board Set SE8500HW4 clock tree is generated from a single CK409 with spread spectrum capability. The CK409 generates multiple copies of differential pair high-speed clocks. Low skew DB800 buffers generate additional copies. The FSB clocks must be length-matched. Skew control is also required on the 166HMz MPCLK going to the XMBs and NB, the 66MHz Hub link clocks, and the legacy / LPC 33MHz clocks.
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Intel® Server Board Set SE8500HW4 8.6 Electrical Specifications Programmable Logic Devices The Intel® Server Board Set SE8500HW4 has three Programmable Logic Devices (PLDs) for fundamental logic on the Mainboard, including power, reset, hot-plug, and miscellaneous signaling. Due to the nature of these devices, they are not programmable by an end user. Table 37.
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Electrical Specifications Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 Mechanical and Thermal Specifications 9. Mechanical and Thermal Specifications 9.1 Mechanical Specifications 9.1.1 Mainboard Figure 19. Mainboard Outline and Hole Location Drawing 65 Revision 1.
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Mechanical and Thermal Specifications Intel® Server Board Set SE8500HW4 Figure 20. Mainboard Pin 1 Location Drawing Revision 1.
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Intel® Server Board Set SE8500HW4 9.1.2 Mechanical and Thermal Specifications Memory Board Figure 21. Memory Board Mechanical Outline Drawing Figure 22. Memory Board Pin 1 Location Drawing 67 Revision 1.
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Mechanical and Thermal Specifications 9.2 Intel® Server Board Set SE8500HW4 Thermal Specifications Table 38.
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Intel® Server Board Set SE8500HW4 System BIOS 10. System BIOS The system BIOS is implemented as firmware that resides in flash ROM. It provides hardwarespecific initialization algorithms, basic input/output (I/O) services, and standard Intel Server Board features. The flash ROM also contains firmware for certain embedded devices that are supplied by the device manufacturers and are not covered in this document.
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System BIOS Intel® Server Board Set SE8500HW4 Table 39. Memory Hot Plug Support Under Different Memory Modes Memory Hot Plug Operation Hot-add Maximum Compatibility Supported Maximum Performance Hot-replace Memory Mirroring Supported Memory RAID Supported Supported Hot-upgrade 10.1.1 Supported Sparing Sparing allows for memory to be set aside to replace memory under use when a DIMMs correctable error count has reached a specified threshold.
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Intel® Server Board Set SE8500HW4 10.1.3 System BIOS Maximum Performance The maximum performance mode is the default memory configuration and provides the best performance. With four Memory Boards installed, the BIOS will configure memory as four-way interleaved, across all the Memory Boards. With less than four Memory Boards installed, the BIOS will attempt to configure two-way interleaving. If memory cannot be configured for two-way interleaving, the BIOS will default to one-way.
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System BIOS Intel® Server Board Set SE8500HW4 Redundant Array of Inexpensive Disks (RAID) level 4, where data is striped across three Memory Boards and parity information is kept on the fourth. When one board fails, the memory subsystem operates in non-redundant mode. The data from the remaining three boards is used to reconstruct the data that was on the failed Memory Board.
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Intel® Server Board Set SE8500HW4 System BIOS 10.2 Rolling BIOS The Intel® Server Board Set SE8500HW4 BIOS can be updated while the server is online, as opposed to immediately turning off the server after a BIOS update. This rolling BIOS features is supported by having two copies of the BIOS, the one in use, and a secondary copy, to which an updated BIOS version can be written. When ready, the system can roll forward to the new BIOS.
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System BIOS Intel® Server Board Set SE8500HW4 Processor installed (status only, indicates processor has passed the BIOS POST). Processor failed. The processor may have failed FRB-3, and has been disabled. Processor not installed (status only, indicates the processor socket has no processor). Once a processor is marked failed, it remains marked failed until “Processor Retest” option is chosen in the BIOS Setup.
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Intel® Server Board Set SE8500HW4 10.3.1.4 System BIOS Microcode Update API Recent Intel processors have the capability of correcting specific errata through the loading of an Intel-supplied data block (i.e. microcode update). The BIOS is responsible for storing the update in nonvolatile memory and loading it into each processor during POST. The BIOS will allow a number of microcode updates to be stored in the Flash, limited by the amount of free space available.
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System BIOS Intel® Server Board Set SE8500HW4 not being able to set the desired configuration during POST, the BIOS reports this error and continues booting with the maximum performance configuration. During a hot insertion operation, if the bad DIMM(s) from the memory test results in the system not being able to set the desired memory mode during runtime, the BIOS rejects the new Memory Board addition request and powers down the newly inserted board.
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Intel® Server Board Set SE8500HW4 System BIOS DIMM bank’s uncorrectable error count. If the error count is less than 10 per hour, the BIOS reports the uncorrectable ECC error to the SEL. When the DIMM uncorrectable error count reaches 10, BIOS lights the bad DIMMs LEDs and disables the DIMM bank for subsequent boots. The system continues to function from redundant memory. Multiple consecutive uncorrectable ECC errors may cause a XMB fail condition and the entire Memory Board to be disabled.
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System BIOS 10.3.4 Intel® Server Board Set SE8500HW4 Operating System ® The Intel Server Board Set SE8500HW4 BIOS provides another timer that acts after the processor FRB stages have completed. By enabling this option in the BIOS Setup, the system BIOS will enable a timer in the BMC with the requested number of minutes. This OS Boot Timer option is disabled by default. It is the responsibility of the operating system, or application, to disable this timer once it has successfully loaded.
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Intel® Server Board Set SE8500HW4 10.4.2 System BIOS Keystroke Mappings During console redirection, the remote terminal (which may be a dumb terminal or a system with a modem running a communication program) sends keystrokes to the local server. The local server passes video back over this same link. The keystroke mappings follow VT-UTF8 format with the following extensions. 10.4.2.1 Setup Alias Keys The ~~and -F key combinations are synonyms for the or “Setup” key.~~
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System BIOS Intel® Server Board Set SE8500HW4 10.5 IPMI Serial/Modem Interface The BMC controls whether the COM2 internal connector is electrically connected to the BMC or the standard serial port of the SIO. Refer to the IPMI 2.0 Specification for more information, with Intel® Server Board Set SE8500HW4-specific implementation described in this section. 10.5.1 Channel Access Modes The BIOS supports the four different channel access modes described in the IPMI 2.0 Specification. 10.5.
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Intel® Server Board Set SE8500HW4 System BIOS 10.6 Wired For Management Wired for Management (WFM) is an industry-wide initiative to increase overall manageability and reduce total cost of ownership by allowing a server to be managed over a network. To meet WFM requirements, the system BIOS supports the System Management BIOS Reference Specification. 10.6.1 PXE BIOS Support The BIOS will support EFI PXE implementation with the Universal Network Device Interface driver included on the network card.
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System BIOS Intel® Server Board Set SE8500HW4 < This page intentionally left blank. > Revision 1.
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Intel® Server Board Set SE8500HW4 BIOS User Interface 11. BIOS User Interface 11.1 Overview There are two types of consoles used for displaying the user interface, graphical or textual. Graphics consoles are in 800x600 mode (pixels). Text consoles are 80 characters x 25 lines. Console output is partitioned into three areas, the System Activity/State, Logo/Diagnostic, and Current Activity windows. The System Activity Window displays information about the current state of the system.
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BIOS User Interface 11.1.3 Intel® Server Board Set SE8500HW4 Current Activity Window The bottom portion of the screen is reserved for the Current Activity Window. On a graphics console the screen is 800x95. On a text console the window is 80x5. 11.2 System Diagnostic Screen The diagnostic screen is the console area where boot information, options, and diagnostic utilities are displayed. All built in utilities use this area in a similar manner to provide for consistent user interaction.
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Intel® Server Board Set SE8500HW4 BIOS User Interface 11.3 Systems Options Menu Screen Table 41. System Options Menu Item Continue Booting Options n/a Default n/a Help Text Select this to boot from the first boot option now. Comment Boot Manager n/a n/a Select this to boot from one of the available boot options. To modify these Boot Options, select Boot Maintenance Manager option in System Options Menu. Selects Boot Options submenu.
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BIOS User Interface Intel® Server Board Set SE8500HW4 11.5 Boot Maintenance Manager Table 43. Boot Maintenance Manager Menu Item Boot Options Options n/a Default n/a Help Text Modify the system boot order and add/delete Boot Options. System reboot is required after any Boot Option change. Comment Link to Boot Options menu Driver Options n/a n/a Modify the EFI driver Boot options Link to Driver Options menu Set Time out Value n/a n/a Modify the automatic boot timeout value.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 45. Change Boot Order Menu Item F2= Previous Page Options Default Help Text Go back to Main Page Change this option’s order (Repeats ‘n’ times for number of devices) Apply Changes Varies varies Other options will change accordingly Comment Takes back to the previous page Select the Boot Options to define the Boot Order. Discard Changes Table 46.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 47. Delete Boot Option Menu Item F2= Previous Page Options Default Help Text Comment Takes back to the previous page Go back to Boot Maintenance Manager Screen Go Back To Main Page n/a n/a Go Back To Main Page String specifying a boot option that can be deleted. (Repeats ‘n’ times for number of drivers) [ ] or [X] [] String specifying boot option. May not be present for some boot options.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 49.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 51.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 54.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 56. Add Driver Option Using Handle Menu Item F2= Previous Page Options Default Go Back To Main Page n/a n/a String specifying a driver option that can be added. (Repeats ‘n’ times for number of drivers) n/a n/a Select this option to add it as a Driver Option. Whether any options appear and what they are varies with system configuration. Once an option is selected, all other options will disappear.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 57. Delete Driver Option Menu Item F2= Previous Page Options Default Help Text Comment Takes back to the previous page Go back to Boot Maintenance Manager Screen Go Back To Main Page n/a n/a Go Back To Main Page String specifying 1st driver option that can be deleted. (Repeats ‘n’ times for number of drivers) [ ] or [X] [] String specifying driver option. May not be present for some driver options.
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BIOS User Interface Item F2= Previous Page Intel® Server Board Set SE8500HW4 Options Default Help Text Go back to Main Page Comment Takes back to the previous page returns to the main page Table 59. Set Time Out Value Menu Item F2 = Previous Page Go Back to Main Page Options n/a Default n/a Auto Boot Time -Out varies 10 Apply Changes Discard Changes n/a n/a n/a n/a Help Text Go Back to Main Page Comment Go back to Boot Maintenance Manager Screen Auto boot timeout value in seconds.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Functional Area Item Specific Help Area. Description The Item Specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item. Help information includes the meaning and usage of the item, allowable values, effects of the options, etc.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Key + Option Change Value Description The plus key on the keypad is used to change the value of the current menu item to the next value. This key scrolls through the values in the associated pick list without displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code than the plus key on the other keyboard, but will have the same effect.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 63. Time and Date Menu Setup Item BIOS Version Options N/A Default N/A Help Text N/A Comment Displays the current the BIOS version (excluding the build time and date). as per description in Section titled BIOS Identification String. System Date [DD/MM/YYYY ] N/A Month valid values are 1 to 12. Day valid values are 1 to 31. Year valid values are 1998 to 2099. Help text depends on the subfield selected (Month, Day, or Year).
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 65. Processor #n Information Menu Setup Item Processor Family Options Maximum Frequency Cache Size Default Help Text Identifies family or generation of the processor. Comment Info Only Maximum frequency the processor core supports. Info Only Size of the processor cache.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 67. Configure System RAS and Performance Menu Setup Item Hardware Memory Test Option Enabled/ Disabled Default Enabled Help Text If enabled, memory will be tested using hardware based engines on each board. Patrol Scrub Enabled/ Disabled Enabled Enable hardware patrol scrub to clean correctable errors.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 68. View Memory Configure Details Menu Setup Item Configuration Option Default Help Text Help Text for Max Performance This 4-way interleave configuration provides the maximum performance. To get maximum performance f boards of same size should be installed. (A:B:C:D) Comment Info Only.
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Intel® Server Board Set SE8500HW4 Setup Item Option BIOS User Interface Default Help Text possible with the current installed memory. Comment Sparing Indicates whether the configuration supports sparing. Info Only Hot Replace Indicates whether configuration allows memory to be replaced while system is running. Info Only Hot Add Indicates whether the configuration allows memory to be added while the system is running.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Setup Item Option Default Help Text has been reported as failed; Comment Table 70. DIMM Labels Menu Label DIMM1A Rank 1/2 Size Size in MB or GB Status See Option cell in previous table DIMM1B 1/2 Size in MB or GB See Option cell in previous table DIMM2A 3/4 Size in MB or GB See Option cell in previous table DIMM2B 3/4 Size in MB or GB See Option cell in previous table Table 71.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 73. Mass Storage Menu Setup Item Enable Onboard SCSI Option Enabled/ Disabled RAID Activation Key Installed/Not Installed Default Enabled Help Text If Disabled, the embedded SCSI device is turned off and device is inaccessible to the OS. Comment Grayed out if ROMB is enabled, If Intel® RAID Activation Key is installed, Intel® RAID On Motherboard (ROMB) option is activated.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 74. LAN Menu Setup Item Enable Onboard NIC Option Enabled/ Disabled Default Enabled Help Text If disabled, both channels of the embedded LAN are turned off and the device is inaccessible to the OS. Comment Enable Onboard NIC ROM Enabled/ Disabled Enabled If enabled, the Option ROM for the Onboard LAN is executed.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 77. Serial Ports Menu Setup Item COM 1 Enable Option Enabled/ Disabled Default Enabled Help Text Enables or disables COM1 port. Address 3F8/2F8/3E8/ 2E8 3F8 Selects the base I/O address for COM1. IRQ 3/4 4 Selects the Interrupt Request line for COM1. Comment Table 78. PCI Menu Setup Item Enable Slot 1 ROM Option Enabled/ Disabled Default Enabled Help Text Enables/Disables Option ROM scan of the device in PCI slot 1.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 79. Server Management Menu Setup Item Console Redirection Option Default Help Text Examine and set console redirection parameters. Comment Link to Setup Utility\Server Management\Console Redirection N/A Examine Field Replaceable Units (FRU) parameters. Link to Setup Utility\Server Management\FRU Information N/A N/A Examine and set System LAN Management options.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 81. COM1 Console Redirection Menu Setup Item BIOS Console Redirection Option Enabled/ Disabled Default Disabled Help Text Enables performing server management tasks over the serial port. Flow Control None RTS/CTS XON/XOFF CTS/RTS + CD None Selects serial port communication protocol handshaking type. Baud Rate 9600/19.2K/38.4 K/57.6K/115.2K 19.2K Selects serial port transmission speed. The speed must be matched on the other side.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Setup Item Option Controller> Default Help Text Comment firmware. Table 83. LAN Management Menu Setup Item LAN Controller 1: Option N/A N/A Default N/A Help Text Comment Title for next items Static IP Enable Enabled/ Disabled Allows Host and Router IP addresses to be manually specified. If disabled, the IP addresses are automatically assigned by the system. Host IP Address <000.000.0 00.
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Intel® Server Board Set SE8500HW4 BIOS User Interface Table 85. FRB Information Menu Setup Item Processor # Information Option Default Help Text Processor Detailed Information. FRB-2 Enable Enabled/ Disabled Enabled If enabled, the BMC will reset the system if the BIOS does not complete the Power On Self Test before the FRB-2 timer expires. OS WD Timer Enable Enabled/ Disabled Disabled If enabled, the timer starts when the system begins to boot an Operating System.
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BIOS User Interface Intel® Server Board Set SE8500HW4 Table 87. Save, Restore and Exit Menu Setup Item Save Changes and Exit Option Default Help Text Apply current values and exit the BIOS Setup. Comment User is prompted for confirmation only if any of the setup fields were modified. Discard Changes and Exit Ignore changes made to values and exit the BIOS Setup. User is prompted for confirmation only if any of the setup fields were modified.
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Intel® Server Board Set SE8500HW4 Error Handling 12. Error Handling 12.1 LEDs 12.1.1 POST Progress LEDs The BIOS provides the current stage of the POST process via a block of eight LEDs. The LEDs are shown in Table 88. Table 88. POST Progress LED Location and Example LED Reference Designator DS7D2 Bit 7 (MSB) DS7D3 6 Example: Initialize Memory DS7D4 5 DS7D5 4 On DS7D6 3 DS7E1 2 DS7E2 1 On DS7E3 0 (LSB) On 0x27 On Table 89.
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Error Handling Code 0x530x57 Intel® Server Board Set SE8500HW4 Description Reserved for PCI Bus USB: 0x58 Resetting USB bus 0x59 Reserved for USB devices SATA: 0x5A Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS: 0x5C Resetting SMBUS 0x5D Reserved for SMBUS Local Console: 0x70 Resetting the video controller (VGA) 0x71 Disabling the video controller (VGA) 0x72 Enabling the video controller (VGA) Remote Console: 0x78 Resetting the console controller 0x79 Disabling the
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Intel® Server Board Set SE8500HW4 Error Handling Code 0xE2 Description Initial memory found, configured, and installed correctly 0xE, 0xE3 Reserved for initialization module use (PEIM) DXE Core: 0xE4 Entered EFI driver execution phase (DXE) 0xE5 Started dispatching drivers 0xE6 Started connecting drivers DXE Drivers: 0xE7 Waiting for user input 0xE8 Checking password 0xE9 Entering the BIOS setup 0xEA Flash update 0xEE Calling Int 19. One beep unless silent boot is enabled.
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Error Handling Intel® Server Board Set SE8500HW4 12.2 Beeps Prior to system video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code will be followed by a user visible code on POST progress LEDs. Table 91. Beep Codes Beeps 1 Error Message Fatal error Description System halted because of an unspecified fatal error that was detected. 2 Processor error System halted because a fatal error related to a processor was detected.
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Intel® Server Board Set SE8500HW4 Error Handling 12.3 POST Messages The following table describes error codes, the associated error message, and the system handling of the error. If the Warn is “Yes”, the error is of low consequence and will have little impact on system functionality. If the Log is “Yes”, the event will be stored in the system error log (SEL). If the Display is “Yes”, the error message will be displayed to the console(s).
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Error Handling Intel® Server Board Set SE8500HW4 Code 8198 Message OS boot watchdog timer failure Severity Major Response Pause 0192 L3 cache size mismatch Major Pause 0193 CPUID, Processor stepping are different Major Pause 0194 CPUID, Processor family are different Major Pause 0195 Front side bus mismatch. Major Pause 0196 CPUID, Processor Model are different Major Pause 81A0 Intel® Management Module firmware and FRUSDR update required.
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Intel® Server Board Set SE8500HW4 Error Handling Code 8539 Message Board: D, DIMM: 1B Memory not configured Severity Major Response Pause 853A Board: D, DIMM: 2A Memory not configured Major Pause 853B Board: D, DIMM: 2B Memory not configured Major Pause 8540 Board: A, DIMM: 1A Memory disabled Major Pause 8541 Board: A, DIMM: 1B Memory disabled Major Pause 8542 Board: A, DIMM: 2A Memory disabled Major Pause 8543 Board: A, DIMM: 2B Memory disabled Major Pause 8548 Board: B, DIMM
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Error Handling Intel® Server Board Set SE8500HW4 Code 8591 Message Board: C, DIMM: 1B Memory correctable ECC error Severity Major Response Pause 8592 Board: C, DIMM: 2A Memory correctable ECC error Major Pause 8593 Board: C, DIMM: 2B Memory correctable ECC error Major Pause 8598 Board: D, DIMM: 1A Memory correctable ECC error Major Pause 8599 Board: D, DIMM: 1B Memory correctable ECC error Major Pause 859A Board: D, DIMM: 2A Memory correctable ECC error Major Pause 859B Board: D,
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Intel® Server Board Set SE8500HW4 Error Handling Code 85E9 Message Board: B Memory not configured Severity Major Response Pause 85F1 Board: C Memory not configured Major Pause 85F9 Board: D Memory not configured Major Pause 85FC System Memory bad or missing Major Pause 85FD System Memory not configured Major Pause 119 Revision 1.
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Reference Documents Intel® Server Board Set SE8500HW4 Reference Documents Advanced Configuration and Power Interface Specification, Revision 1.0b. Intelligent Chassis Management Bus (ICMB) Specification, Version 1.0, Rev 1.20. Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0. Intelligent Platform Management Interface Specification, Version 2.0. Microsoft Headless Design Guidelines. System Management BIOS Reference Specification. Revision 1.