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Intel® Server Board SDS2

Technical Product Specification

Order Number: A85874-002

Revision 1.2

December 2, 2002

Enterprise Platforms and Services Marketing

Summary of content (145 pages)

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Intel® Server Board SDS2 Technical Product Specification Order Number: A85874-002 Revision 1.
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Revision History Intel® Server Board SDS2 Revision History Date 9/20/2001 Revision Number 1.0 Modifications 5/15/2002 1.1 Added Section 13: Errata. Corrected miscellaneous document errors. Added Table 6.2.5.4: Baseboard Management Controller (BMC) Beep Code Generation. 12/2/02 1.2 Added Errata 19-37 that are corrected with FAB5. Updated Table 6.2.5.4. Added Table 25. Initial release. ii Revision 1.
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Intel® Server Board SDS2 Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server Board SDS2 Table of Contents 1. Introduction .............................................................................................................................1 2. Architecture .............................................................................................................................2 3. Processor and Chipset ..........................................................................................................4 3.1 Processors ..............
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Intel® Server Board SDS2 4.6.2 4.7 Table of Contents BIOS Flash..................................................................................................................20 Interrupt Routing ...............................................................................................................20 4.7.1 Legacy Interrupt Routing.............................................................................................20 4.7.2 APIC Interrupt Routing .....................................
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Table of Contents 6.3.4 6.4 Intel® Server Board SDS2 Clearing CMOS...........................................................................................................67 Flash Update Utility ...........................................................................................................67 6.4.1 Loading the System BIOS ..........................................................................................67 6.4.2 User Binary Area....................................................
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Intel® Server Board SDS2 8.9 Table of Contents Connector Manufacturers and Part Numbers ..................................................................87 9. Jumpers..................................................................................................................................88 9.1 System Configuration Jumpers........................................................................................88 9.2 Performing CMOS Clear, BIOS Recovery, and BMC Force Update ...................
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Table of Contents Intel® Server Board SDS2 5. Intel® & ICP Vortex* RAID Controllers will cause the Intel® Server Board SDS2 to halt during POST when the BIOS Logo screen is enabled.............................................................109 6. Intel® Server Board SDS2 CD-ROM issues..................................................................110 7. NIC driver set 5.12 v.2.3.15 for UnixWare* 7.1.1 drops DPC LAN connection..............111 8. NIC driver set 5.12 v.5.41.
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Intel® Server Board SDS2 Table of Contents 34. Peer-to-peer PCI transactions are not supported between the CIOB-controlled 64-bit PCI bus and the legacy 32-bit PCI bus controlled by the HE-SL north bridge .........................125 35. SDS2 PCI slot current levels supported by the 5V rail...................................................125 36. OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu125 Glossary...................................................................
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List of Figures Intel® Server Board SDS2 List of Figures Figure 1. SDS2 Server Board Block Diagram .................................................................................1 Figure 2. SDS2 Memory Bank Layout..............................................................................................7 Figure 3. SDS2 Interrupt Routing Diagram (CSB5 Internal)..........................................................22 Figure 4. SDS2 Interrupt Routing Diagram .........................................
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Intel® Server Board SDS2 List of Tables List of Tables Table 1. SDS2 Intel® Pentium® III Processor Support Matrix.........................................................4 Table 2. Memory DIMM Pairs ...........................................................................................................7 Table 3. I2C Addresses for DIMM Slots............................................................................................8 Table 4. PCI Bus Segment Characteristics...............................
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List of Tables Intel® Server Board SDS2 Table 32. Main Menu Selections ....................................................................................................55 Table 33. Primary Master and Slave IDE Submenu Selections ....................................................56 Table 34. Processor Settings Submenu Selections......................................................................57 Table 35. Advanced Menu Selections ....................................................................
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Intel® Server Board SDS2 List of Tables Table 66. IDE 40-pin Connector Pin-out ........................................................................................82 Table 67. Stacked Three-port USB Connector Pin-out .................................................................82 Table 68. 10-pin USB Connection Header (2 x 5) Pin-out .............................................................83 Table 69. 34-pin Floppy Connector Pin-out ............................................................
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List of Tables Intel® Server Board SDS2 < This page intentionally left blank. > xiv Revision 1.
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Intel® Server Board SDS2 1. Introduction Introduction This chapter provides an architectural overview of the Intel® SDS2 Server Board. It provides a view of the functional blocks and their electrical relationships. The figure below shows the functional blocks of the Server Board and the plug-in modules that it supports.
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Architecture 2. Intel® Server Board SDS2 Architecture The SDS2 Server Board is a monolithic printed circuit board that can accept two Intel® Pentium ® III processors using the Socket 370 FCPGA2 package. The SDS2 Server Board complies with the Entry SSI version 1.0 and ATX version 2.03 (12 inch x 13 inch) form-factor. It is designed around the Server Works* ServerSet* III HE-SL chipset.
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Intel® Server Board SDS2 • • • • • • • • • Architecture 64-bit, 66-MHz 3.3 V full-length PCI segment C (P64-C) with one embedded device - Dual Channel Wide Ultra160 SCSI controller: Adaptec* AIC-7899W - Two 64-bit 3.
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Processor and Chipset 3. Intel® Server Board SDS2 Processor and Chipset The Server Works* ServerSet III HE-SL chipset provides the 36-bit address, 72-bit data (64-bit data + 8-bit ECC) processor host bus interface, operating at 133 MHz in the AGTL signaling environment. The HE-SL North Bridge provides an integrated memory controller, the interface to 32-bit, 33-MHz Rev 2.2 compliant PCI bus, and two Inter-Module Bus interfaces.
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Intel® Server Board SDS2 Processor and Chipset Pentium III – Tray SL5XL Intel Pentium III – Boxed FCPGA2 843849 1.4GHZ/133MHz 512KB tA1 06B1h Yes SL5XL Notes: • All processor sockets must be populated with either a processor or a terminator module. The BMC will not allow DC power to be applied to the system unless both processor sockets contain a properly seated processor or terminator module. • Processors should be populated in the sequential order.
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Processor and Chipset 3.1.1 Intel® Server Board SDS2 Processor Voltage Regulator Module (VRM) The SDS2 Server Board has dual, on board, RM circuitry to support the two processors. The circuit is compliant with the VRM8.5 specification and provides a maximum of 60A, which will support the currently available processors and future releases of the Pentium III processors.
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Intel® Server Board SDS2 Processor and Chipset Table 2. Memory DIMM Pairs Memory DIMM DIMM PAIR Row DIMM1A, DIMM1B 1 1, 2 DIMM2A, DIMM2B 2 3, 4 DIMM3A, DIMM3B 3 5, 6 DIMM Pair 1 DIMM Pair 2 DIMM Pair 3 Figure 2. SDS2 Memory Bank Layout Revision 1.
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Processor and Chipset 3.2.2 Intel® Server Board SDS2 I2C Bus An I2C* bus is between the BMC and the six DIMM slots. This bus is used by the system BIOS to retrieve DIMM information needed to program the HE-SL memory registers which are required to boot the system. The following table provides the I2C addresses for each DIMM slot. Table 3. I2C Addresses for DIMM Slots 3.
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Intel® Server Board SDS2 3.3.1 Processor and Chipset CNB20HE-SL Champion North Bridge The Champion North Bridge Rev 2.0 High End Super Lite (CNB20HE-SL) is the third generation product in the Server Works Champion North Bridge Technology. The HE-SL is a 644-pin ballgrid array (BGA) device and uses the proven components of previous generations like the Pentium Pro Bus interface unit, the PCI interface unit, and the SDRAM memory interface unit.
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Processor and Chipset 3.3.2 Intel® Server Board SDS2 CIOB20 Champion I/O Bridge The Champion I/O Bridge (CIOB) is a 352-pin ball-grid array device and provides an integrated I/O bridge that provides a high-performance data flow path between the IMBus and the 64-bit I/O subsystem. This subsystem supports peer 64-bit PCI segments. Because it has multiple PCI interfaces, the CIOB can provide large and efficient I/O configurations.
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Intel® Server Board SDS2 I/O Subsystem 4. I/O Subsystem 4.1 PCI Subsystem The primary I/O bus for SDS2 DP Server Board is PCI, with three PCI bus segments. The PCI buses comply with the PCI Local Bus Specification, Rev 2.2. The P32-A bus segment is directed through the HE-SL North Bridge while the two 64bit segments, P64-B and P64-C, are directed through the CIOB20 I/O Bridge. The table below lists the characteristics of the three PCI bus segments. Table 4.
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I/O Subsystem Intel® Server Board SDS2 Table 5. P32-A Configuration IDs IDSEL Value 4.1.1.2 Device 18 ATI RAGE XL Video Controller 19 Intel 82550 Fast Ethernet Controller 1 20 Intel 82550 Fast Ethernet Controller 2 24 PCI Slot 3 25 PCI Slot 4 31 CSB5 South Bridge P32-A Arbitration P32-A supports seven PCI masters (ATA RAGE XL, two Intel 82550s, PCI masters from slots 3 and 4, CSB5, and HE-SL). All PCI masters must arbitrate for PCI access, using resources supplied by the HE-SL.
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Intel® Server Board SDS2 I/O Subsystem Table 4. P64-B Configuration IDs IDSEL Value Device 24 PCI Slot 1 25 PCI Slot 2 Table 5. P64-C Configuration IDs IDSEL Value 4.1.2.2 Device 20 Adaptec AIC-7899W SCSI Controller 24 PCI Slot 5 25 PCI Slot 6 P64-B Arbitration P64-B supports three PCI masters (PCI masters from slots 1 and 2, and CIOB). All PCI masters must arbitrate for PCI access, using resources supplied by the CIOB. The following table defines the arbitration connections. Table 7.
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I/O Subsystem 4.1.2.4 Intel® Server Board SDS2 Zero Channel RAID (ZCR) Capable PCI Slot 6 The SDS2 Server Board supports zero-channel RAID controller on PCI Slot 6. This add-in card leverages the on-board SCSI controller along with its own built-in intelligence to provide a complete RAID controller subsystem on-board.
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Intel® Server Board SDS2 I/O Subsystem Table 9.
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I/O Subsystem 4.4.1 Intel® Server Board SDS2 NIC Connector and Status LEDs The 82550 drives LEDs on the network interface connector to indicate link/activity on the LAN and 10-Mbps or 100-Mbps operation. • The green LED indicates a network connection when lighted solidly and TX/RX activity when blinking. • The amber LED indicates 100-Mbps a network connection when lighted solidly and TX/RX activity when blinking. 4.
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Intel® Server Board SDS2 • • • I/O Subsystem The scatter / gather mechanism supports both DMA and PIO IDE drives and ATAPI devices Support for ATA and ATAPI, PIO Mode 0, 1, 2, 3, 4, DMA Mode 0, 1, 2, and Ultra DMA Mode 0, 1, 2, 3, 4, 5 The IDE drive transfer rate is capable of up to ATA-100 (100 MB/sec per channel) 4.5.3 USB Interface The CSB5 contains a USB controller and four USB hubs. The USB controller moves data between main memory and the four USB connectors.
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I/O Subsystem Pad Intel® Server Board SDS2 GPIO Name Description Y19 N_NVRAMCLR Input from jumper to be in BIOS Recovery mode in case of corruption V17 N_PASSDIS_00 Input from jumper to clear password assignments U16 N_CMOSCLR_00 Input from jumper to clear setup info in CMOS T20 N_F3SETUPEN_00 Input from jumper to to be in special test mode (manufacturing only) T19 N_BMC_SCIN Input from BMC of SCI event T18 N_BMCISPMD_00 Input from jumper to to be in special test mode (manufacturing on
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Intel® Server Board SDS2 Pin # I/O Subsystem Signal Name Description 35 N_BMC_SWIN 36 N_BMCPWRN Power LED from BMC 37 N_EXTEN_00 External Event 38 N_SUPERSCI_00 System Control Interrupt used to detect wake-up events 45 N_SIO_CLK_RTC_BMC Real Time Clock output to BMC 49 N_P2_PME Power Management Event from PCI Bus (P64-B segment) 50 N_P3_PME Power Management Event from PCI Bus (P64-C segment) 51 N_FP_PWR_LED+00 Power LED indicator to Front Panel 52 N_LAN_PME Power Management Eve
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I/O Subsystem 4.6.2 Intel® Server Board SDS2 BIOS Flash The SDS2 Server Board incorporates a Fairchild* 29LV008B 8Mbit Flash ROM. The flash device is connected through the X-bus of the CSB5. 4.7 Interrupt Routing The SDS2 Server Board interrupt architecture implements both PC-compatible PIC mode and APIC mode interrupts through the use of the integrated I/O APICs in the CSB5. 4.7.1 Legacy Interrupt Routing For PC-compatible mode, the CSB5 provides two 82C59-compatible interrupt controllers.
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Intel® Server Board SDS2 I/O Subsystem ISA Interrupt Description INTR Processor interrupt NMI NMI to processor IRQ1 Keyboard interrupt IRQ3 Serial port 1 or 2 interrupt from SIO device IRQ4 Serial port 1 or 2 interrupt from SIO device IRQ5 IRQ6 Floppy Controller IRQ7 IRQ8_L Real Time Clock interrupt IRQ9 IRQ10 IRQ11 IRQ12 PS/2 Mouse interrupt IRQ14 Primary channel IDE interrupt SMI* System Management Interrupt.
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I/O Subsystem Intel® Server Board SDS2 IOAPIC 0 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 SCAN2 IRQ0-15 PCI Cycle INT Mapping 8259 PIC 15 PCIIRQ0 PCIIRQ1 PCIIRQ2 PCIIRQ3 PCIIRQ4 PCIIRQ5 PCIIRQ6 PCIIRQ7 PCIIRQ8 PCIIRQ9 PCIIRQ10 PCIIRQ11 PCIIRQ12 PCI Cycle SCAN0 PCIIRQ0PCIIRQ15 IOAPIC 1 MASK for PCIIRQ0-15 1 PCIIRQ PCIIRQ16 PCIIRQ17 PCIIRQ18 PCIIRQ19 PCIIRQ20 PCIIRQ21 PCIIRQ22 PCIIRQ23 PCIIRQ24 PCIIRQ25 PCIIRQ26 PCIIRQ27 PCIIRQ28 PCI Cycle SCAN1 PCIIRQ16PCIIRQ31 IOAPIC
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Intel® Server Board SDS2 Timer I/O Subsystem Super I/O Keyboard Cascade Serial Port2/ISA Serialized IRQ Interface Serial Port1/ISA ISA Floppy/ISA ISA RTC SCI/ISA ISA Mouse/ISA Coprocessor Error P_IDE/ISA PCI Clock S_IDE/ISA 33 MHz PCIIRQ0 SCSI Ch B PCIIRQ1 NIC 1 PCIIRQ2 NIC 2 PCIIRQ3 Video PCIIRQ4 Slot1 INTA PCIIRQ5 Slot2 INTA PCIIRQ6 Slot3 INTA PCIIRQ7 Slot4 INTA PCIIRQ8 Slot5 INTA PCIIRQ9 Slot6 INTA PCIIRQ10 INTBCD PCIIRQ11 INTBCD PCIIRQ12 INTBCD PCIIRQ13 N/C PCIIRQ1
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I/O Subsystem Intel® Server Board SDS2 Slot 6 Slot 5 Slot 4 Slot 3 Slot 2 Slot 1 PCI IRQ 10 PCI IRQ 9 PCI IRQ 8 PCI IRQ 7 PCI IRQ 6 INTA PCI IRQ 5 INTB PCI IRQ 13 INTC PCI IRQ 11 INTD PCI IRQ 12 NIC 1 PCI IRQ 2 NIC 2 PCI IRQ 3 VIDEO PCI IRQ 4 PORT A PCI IRQ 0 SCSI PCI IRQ 1 PORT B ZCR Present Figure 5. SDS2 PCI Interrupt Mapping Diagram 24 Revision 1.
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Intel® Server Board SDS2 5. Server Management Server Management The SDS2 server management features are implemented using the Sahalee Server Board Management Controller chip. The Sahalee BMC is an ASIC packaged in a 156-pin BGA that contains a 32-bit RISC processor core and associated peripherals. The following diagram illustrates the SDS2 server management architecture. A description of the hardware architecture follows. Revision 1.
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Speaker Network Activity LEDs Power LED Identify LED Drive Activity/Fault LED Intel® Server Board SDS2 Fault Status LED Power Button Reset Button System Identify Button Sleep Button Front Panel NMI Switch Chassis Intrusion Server Management Front Panel Connectors BASEBOARD DIMM SPD (6) spkr Aux.
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Intel® Server Board SDS2 5.1 Server Management Sahalee Baseboard Management Controller The Sahalee BMC contains a 32-bit RISC processor core and associated peripherals used to monitor the system for critical events. The Sahalee BMC, packaged in a 156-pin BGA, monitors all power supplies, including those generated by the external power supplies and those regulated locally on the Server Board.
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Server Management Pin Intel® Server Board SDS2 Signal Name Description 13 N_SM2_CLK Serial Bus Clock 14 N_SM2_DATA Serial Bus Data 18 N_ADM_FAN_PWM Pulse-width modulated output for control of fan speed 19 N_RST_BMCRST_L Power-on Reset with minimum of 200ms pulse width 29 3VSB Monitors 3V Standby supply 22 5VSB Monitors 5V Standby supply 7 3V Monitors 3V supply 30 5V Monitors +5V supply 31 -12V Monitors –12V supply 32 +12v Monitors +12V supply 33 VCCORE1 Monitors CPU1 cor
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Intel® Server Board SDS2 Server Management Pin Signal Name Description C14 N_FAN6_SENSE_P Rear System Fan 2 Speed L12 N_MEM_ALERT_L Memory ECC Error Detect M12 N_BMC_SECUREMODE Secure Mode Detect Note: For a complete listing of BMC sensors, please refer to SDS2 Baseboard Management Controller External Product Specification. ADM1026 Sahalee Figure 7. SDS2 Locations of ADM1026 and Sahalee 5.1.
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Server Management 5.2 Intel® Server Board SDS2 System Reset Control Reset circuitry on the SDS2 Server Board looks at resets from the front panel, CSB5, ITP, and processor subsystem to determine proper reset sequencing for all types of reset. The reset logic is designed to accommodate a variety of ways to reset the system, which can be divided into the following categories: • • • Power-up reset Hard reset Soft (programmed) reset The following subsections describe each category of reset. 5.2.
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Intel® Server Board SDS2 Server Management Table 17. IPMB Bus Devices Function Voltage Address SCSI HSBP-A 5VSB 0xC0 SCSI HSBP-B 5VSB 0xC2 OEM Connector 5VSB N/A Notes In addition to the “public” IPMB, the Sahalee BMC also has five private I2C busses. Four of these are used on the Server Board. The Sahalee BMC is the only master on the private busses. The following table lists all Server Board connections to the Sahalee BMC private I2C busses. Table 18.
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Server Management Function Voltage Intel® Server Board SDS2 Address CSB5 3.3 V 0xC2 DIMM 1 3.3 V 0xA0 DIMM 2 3.3 V 0xA2 DIMM 3 3.3 V 0xA4 DIMM 4 3.3 V 0xA6 DIMM 5 3.3 V 0xA8 DIMM 6 3.3 V 0xAA PCK2001M 3.3 V 0xD2 Notes South Bridge Clock Buffers Table 21. Private I2C Bus 4 Devices Function Voltage Address NIC1 3 VSB 0x84 NIC2 3VSB 0x86 5.4 Error Reporting Notes This section documents the types of system bus error conditions monitored by the SDS2 Server Board. 5.4.
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Intel® Server Board SDS2 Server Management uncorrectable errors. In addition, the HE-SL can generate BERR# on unrecoverable ECC errors detected on the processor bus. Unrecoverable errors are routed to NMI by BIOS. 5.4.4 Memory Bus Errors The HE-SL is programmed to generate an SMI on single-bit data errors in the memory array if ECC memory is installed. The HE-SL performs the scrubbing. The SMI handler simply records the error and the DIMM location to the System Event Log.
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Server Management Intel® Server Board SDS2 Setup Utility (F2) can change the AC link mode settings. 34 Revision 1.
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Intel® Server Board SDS2 6. BIOS BIOS This section describes the BIOS-embedded software for the SDS2 server board. The BIOS contains standard PC-compatible basic input/output (I/O) services, system-specific hardware configuration routines and register default settings that are embedded in Flash read-only memory (ROM). This document also describes BIOS support utilities (not ROM-resident) that are required for system configuration and flash ROM update.
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BIOS • • • • 6.2 Intel® Server Board SDS2 OEM customization PCI and Plug and Play (PnP) BIOS interface Console redirection Resource allocation support BIOS Error Handling This section defines how errors are handled by the system BIOS on the SDS2 server board. Also discussed are the role of BIOS in error handling, and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling.
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Intel® Server Board SDS2 BIOS The BIOS logs the following SEL entries. Table 22.
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BIOS Intel® Server Board SDS2 Table 23: Event Request Message Event Data Field Contents Event Trigger Class Discrete Event Data 7:6 00 = Unspecified byte 2 01 = Previous state and/or severity in byte 2 10 = OEM code in byte 2 11 = Sensor specific event extension code in byte 2 5:4 00 = Unspecified byte 3 01 = Reserved 10 = OEM code in byte 3 11 = Sensor specific event extension code in byte 3 3:0 Offset from Event Trigger for discrete event state Event Data 2 7:4 Optional offset from ‘Severity’ E
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Intel® Server Board SDS2 6.2.3.3 BIOS Memory Bus Error The BMC monitors and logs memory errors. The BIOS will configure the hardware to notify the BMC on correctable and uncorrectable memory errors. Uncorrectable errors generate an SMI to stop the system and prevent propagation of the error. The BMC will query the hardware for error information when notified. 6.2.3.4 System Limit Error The BMC monitors system operational limits.
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Intel® Server Board SDS2 Sensor Name Power Unit Status Sensor # BIOS 01h Sensor Type Power Unit 09h Event/ Reading Type Sensor Specific - 6Fh Event Offset Triggers Power Off, Power Cycle, A/C Lost, Power Unit Redundancy 02h Power Unit 09h Generic 0Bh Redundancy Regain Redundancy lost Timer Expired, Watchdog 03h Watchdog2 – 23h Sensor Specific - 6Fh Hard Reset, Power Down, Power Cycle, Timer Interrupt - Secure mode violation attempt, 04h Platform Security Violation Attempt - 06h Sensor
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Sensor Name BIOS Sensor # Intel® Server Board SDS2 Sensor Type Event/ Reading Type Event Offset Triggers BB -12V 10h Voltage – 02h Threshold 01h - BB VBAT 11h Voltage – 02h Threshold 01h - Proc VRM1 12h Voltage – 02h Threshold 01h - Proc VRM2 13h Voltage – 02h Threshold 01h - LVDS SCSI channel 1 terminator 1 14h Voltage – 02h Threshold 01h LVDS SCSI channel 1 terminator 2 15h Voltage – 02h Threshold 01h LVDS SCSI channel 1 terminator 3 16h Voltage – 02h Threshold 01h L
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Intel® Server Board SDS2 Sensor Name Sensor # BIOS Sensor Type Event/ Reading Type Event Offset Triggers Fan Boost Front Panel Temp 3Ch OEM - C7h Threshold 01h - Fan Boost PDB Temp 3Dh OEM - C7h Threshold 01h - Fan Boost Proc 1 Core Temp 3Eh OEM - C7h Threshold 01h - Fan Boost Proc 2 Core Temp 3Fh OEM - C7h Threshold 01h - Tach Fan 1 48h Fan - 04h Threshold 01h - Tach Fan 2 49h Fan - 04h Threshold 01h - Tach Fan 3 4Ah Fan - 04h Threshold 01h - Tach Fan 4 4Bh Fan -
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BIOS Sensor # Intel® Server Board SDS2 Event/ Reading Type Event Offset Triggers 5Bh Power Supply 08h Sensor Specific - 6Fh Presence, Failure, Predictive Fail, A/C Lost Power Supply 3 5Ch Power Supply 08h Sensor Specific - 6Fh Presence, Failure, Predictive Fail, A/C Lost Missing CPU Module 5Eh Module/Board – 15h Digital Discrete - 03h State Asserted Sensor Name Power Supply 2 Sensor Type Presence, Thermal Trip, Proc 1 Status 5Fh Processor 07h Sensor Specific - 6Fh IERR, FRB1, FRB2,
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Intel® Server Board SDS2 Sensor Name DIMM 6 Sensor # BIOS 6Dh Sensor Type Slot Connector - 21h Event/ Reading Type Sensor Specific - 6Fh Event Offset Triggers Fault Status Asserted, Device Installed, Disabled S0 / G0, System ACPI Power State 78h System ACPI Power State – 22h Sensor Specific - 6Fh S1, S4, S5 / G2, G3 Mechanical Off Button 79h Button – 14h Sensor Specific - 6Fh Power Button, Sleep Button, Reset Button System Event 7Ah System Event – 12h Sensor Specific - 6Fh OEM Syste
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Intel® Server Board SDS2 6.2.5 BIOS Error Messages and Error Codes The system BIOS displays error messages on the video screen. Before video initialization, beep codes inform the user of errors. POST error codes are logged in the System Event Log. The BIOS displays POST error codes on the video monitor. 6.2.5.1 ASF Progress Codes The BIOS utilizes ASF Progress Events as described in the ASF Specification, Revision 1.0a from the DMTF. The events that the BIOS supports are shown in the following table.
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BIOS Intel® Server Board SDS2 The following table contains the POST codes displayed during the boot process. A beep code is a series of individual beeps on the PC speaker, each of equal length. The following table describes the error conditions associated with each beep code and the corresponding POST checks point code as seen by a ‘port 80h’ card and LCD. For example, if an error occurs at checkpoint 22h, a beep code of 1-3-1-1 is generated. The “-“ indicates a pause within the sequence.
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Intel® Server Board SDS2 BIOS CP 1C Beeps 20 1-3-1-1 Test DRAM refresh 22 1-3-1-3 Test 8742 Keyboard Controller 24 28 Set ES segment register to 4GB 1-3-3-1 29 Auto size DRAM, system BIOS stops execution here if the BIOS does not detect any usable memory DIMMs Initializes the POST Memory Manager 2A 2C Reason Reset Programmable Interrupt Controller Clear 8 MB base RAM 1-3-4-1 Base RAM failure, BIOS stops execution here if entire memory is bad 2E Test the first 4MB of RAM 2F Initialize ex
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BIOS CP 59 Intel® Server Board SDS2 Beeps Reason Initialize the POST display service 5A Display prompt “Press F2 to enter SETUP” 5B Disable L1 cache during POST 5C Test RAM between 512 and 640k 60 Test extended memory 62 Test extended memory address lines 64 Jump to UserPatch1 66 Configure advanced cache registers 67 Quick init of all AP's early in pos t 68 Enable external and processor caches 69 Initialize the SMM handler 6A Display external cache size 6B Load custom defaults if
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Intel® Server Board SDS2 CP 97 98 BIOS Beeps Reason Fix up Multi Processor table 1-2 Search for option ROMs. One long, two short beeps on checksum failure 99 Check for SMART Drive 9A Shadow option ROMs 9C Set up Power Management 9D Initialize security engine 9E Enable hardware interrupts A0 Set time of day A2 Check key lock A4 Initialize spermatic rate Table 28.
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BIOS 6.2.5.3 Intel® Server Board SDS2 POST Error Codes and Messages The following table defines POST error codes and their associated messages. The BIOS prompts the user to press a key in case of serious errors. Some error messages are preceded by the string "Error” to indicate that the system may be malfunctioning. All POST errors and warnings are logged in the System Event Log unless it is full. Table 29.
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Intel® Server Board SDS2 Code BIOS Error Message Failure Description 0614 COM A config. error - device disabled 0615 COM B configuration changed 0616 COM B config. error - device disabled 0617 Floppy configuration changed 0618 Floppy config. error - device disabled 0619 Parallel port configuration changed 061A Parallel port config.
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BIOS 6.3 Intel® Server Board SDS2 Code 1-5-1-1 FRB failure (processor failure) Reason for Beep 1-5-2-1 Empty Processor 1-5-2-2 No Processor 1-5-2-3 Processor configuration error (e.g., mismatched VIDs) 1-5-4-2 Power fault: DC power unexpectedly lost (power control failures) 1-5-4-3 Chipset control failure 1-5-4-4 Power control fault Setup Utility This section describes the ROM resident Setup utility that provides the means to configure the platform.
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Intel® Server Board SDS2 BIOS Options Menu Each Option Menu occupies the left and center sections of the screen. Each menu contains a set of features. Selecting certain features within a major Option Menu drops you into submenus. Item Specific Help Screen An item-specific help screen is located at the right side of the screen. 6.3.2.
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BIOS Intel® Server Board SDS2 Key F1 Option Help Description Pressing F1 on any menu invokes the g eneral Help window. This window describes the Setup key legend. The up arrow, down arrow, Page Up, Page Down, Home, and End keys scroll the text in this window. Enter Execute Command The Enter key is used to activate sub-menus when the selected feature is a sub-menu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date.
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Intel® Server Board SDS2 6.3.2.3 BIOS Menu Selection Bar The Menu Selection Bar is located at the top of the screen. It displays the various major menu selections available to the user: • • • • • • Main Menu. Advanced Menu. Security Menu. Server Menu. Boot Menu. Exit Menu. These and associated submenus are described below. 6.3.2.3.1 Main Menu Selections The following tables describe the available functions on the Main Menu, and associated submenus. Default values are highlighted. Table 32.
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BIOS Intel® Server Board SDS2 Feature Option Description Spanish Italian French German Table 33. Primary Master and Slave IDE Submenu Selections Feature Type Option Auto None Description Select the byte of device that is attached to the IDE. Channel. If User is selected, the user will need to enter the parameters of IDE device (cylinders, head and sectors). CDROM User ATAPI Removable IDE Removable Other ATAPI CHS format Cylinders 1 to 2048 Number of Cylinders on Drive.
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Intel® Server Board SDS2 Feature Transfer Mode BIOS Standard Option Description Select the method for moving data to/from the drive. FPIO 1 This field is informational only, for Type Auto. FPIO 2 This field is updated to display only the modes supported by the attached device. FPIO 3 FPIO 4 FPIO 3 / DMA 1 FPIO 4 /DMA 2 Ultra DMA Mode Disabled Selects the Ultra DMA mode used for moving data to/from the drive.Autotype the drive toselect the optimum transfer mode.
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BIOS 6.3.2.3.2 Intel® Server Board SDS2 Advanced Menu Selections The following tables describe the menu options and associated submenus available on the Advanced Menu. Please note that MPS 1.4/1.1 selection is no longer configurable. The BIOS always builds MPS 1.4 tables. Table 35. Advanced Menu Selections Feature Memory Configuration Option Description Select sub-menu PCI Configuration Selects sub-menu. I/O Device/peripheral Configuration Selects sub-menu.
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Intel® Server Board SDS2 Extended RAM Step BIOS Disabled Selects the size of step to use during Extended RAM tests. 1 MB 1 KB Every- Location Table 37.
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BIOS Feature Option ROM Scan Intel® Server Board SDS2 Option Enabled Description Enable option ROM scan of the selected device. Disabled 60 Revision 1.
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Intel® Server Board SDS2 BIOS Table 41. I/O Device/Peripheral Configuration Submenu Selections Feature Serial Port 1 Option Disabled Description If set to “Auto,” BIOS or OS configures the port. Enabled Auto Base I/O Address 3F8h Selects the base I/O address for COM port 1. 2F8h 3E8h 2E8h Interrupt 4 Selects the IRQ for COM port 1. 3 Serial Port 2 Disabled If set to “Auto”, BIOS or OS configures the port. Enabled Auto Base I/O Address 3F8h Selects the base I/O address for COM port B.
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BIOS Intel® Server Board SDS2 Table 42. Advanced Chipset Controller Submenu Selections Feature PCI Device Wake On Ring Option Enabled Only controls legacy wake up. May not be present if not supported. Disabled Wake On LAN Enabled Sleep Button Description Selects sub-menu Disabled Only controls legacy wake up. May not be present if not supported. Present Selects the sleep button of the platform. Absent Table 43.
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Intel® Server Board SDS2 BIOS Feature Set Administrative Password Option Press Enter Description When the Enter key is pressed, the user is prompted for a password; press ESC key to abort. Once set, can be disabled by setting to a null string, or clear password jumper on board. Password on boot Disabled If enabled, requires password entry before boot.
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BIOS Intel® Server Board SDS2 Feature Assert NMI on PERR Option Description If enabled, PCI bus parity error (PERR) is enabled and is routed to NMI. Disabled Enabled Assert NMI on SERR Enabled If enabled, PCI bus system error (SERR) is enabled and is routed to NMI. Disabled FRB-2 Policy FRB2 Disable Controls the policy of the FRB-2 timeout. This option determines when the Boot Strap Processor (BSP) should be disabled if FRB-2 error occur. And Detemines when FRB2 stop.
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Intel® Server Board SDS2 BIOS Table 47. Console Redirection Submenu Selections Feature Serial Port Address Option Disabled On-board COM A On-board COM B Baud Rate 9600 Description When enabled, Console Redirection uses the I/O port specified. Choosing “Disabled” completely disables Console Redirection. When Console Redirection is enabled, use the baud rate specified. When EMP is sharing the COM port as console redirection, the baud rate must be set to 19.
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BIOS Intel® Server Board SDS2 Table 49. Hard Drive Selections Option Drive #1 (or actual drive string) Other bootable cards Additional entries for each drive that has a PnP header Description To select the boot drive, use the up and down arrows to highlight a device, then press the plus key (+) to move it to the top of the list or the minus key (–) to move it down. Other bootable cards cover all the boot devices that are not reported to the system BIOS through BIOS Boot specification mechanism.
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Intel® Server Board SDS2 6.3.3 BIOS CMOS Memory Definition The CMOS map is available in the NVRAM.LST file generated for every BIOS release. The CMOS map is subject to change without notice. 6.3.4 Clearing CMOS The BIOS detects the state of the CMOS jumper. If the jumper is set to “CMOS Clear” prior to power-on or a hard reset, the BIOS changes the CMOS and NVRAM settings to a default state. This guarantees the system’s ability to boot from floppy. Password settings are unaffected through CMOS clear.
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BIOS Intel® Server Board SDS2 This file is loaded into the PHLASH program with the /b=. The disk created by the BIOS.EXE program automatically runs “PHLASH /s /b=PLATCXLU.BIN command” in non-interactive mode. For a complete list of PHLASH options, run “PHLASH /h”. Once an update of the system BIOS is complete, the user is prompted for a reboot. The user binary area is also updated during a system BIOS update. User binary can be updated independently of the system BIOS.
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Intel® Server Board SDS2 BIOS 5. Turn on system power. The system boots from the recovery diskette. The BIOS will beep twice when the update process starts. The system will continue to beep while updating the BIOS. If BIOS update completes successfully, the system will stop beeping. If the update fails, the system will sound an alternating pattern of a buzz and a beep. When the flash update completes: 1. Turn off system power. 2. Remove the recovery diskette. 3.
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Clock/Voltage Generation and Distribution Intel® Server Board SDS2 7. Clock/Voltage Generation and Distribution 7.1 Clock All buses on the SDS2 Server Board operate using synchronous clocks. Clock synthesizer/driver circuitry on the Server Board generates clock frequencies and voltage levels as required, including the following: • • • • • • 133 MHz at 2.5 V logic levels: For CPU1, CPU2, HE-SL, DIMM Sockets and the ITP port 66 MHz at 3.
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Revision 1.2 Order Number: A85874-002 PCI 66MHz CLK PCI 33MHz CLK 14 MHz 48 MHz APIC CLK HOST CLK 14.
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Clock/Voltage Generation and Distribution 7.2 Intel® Server Board SDS2 Voltage The system power supply provides +3.3V, +5V, +12V, -12V, and +5VSB and voltage regulators on the Server Board are used to create the following voltages: • • • • • +3.3VSB VCORE for the CPUs VTT for the CPUs +2.5V for the chipsets +1.8V for the onboard SCSI The following figure illustrates voltage generation and distribution on the SDS2 Server Board. 72 Revision 1.
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Revision 1.2 Order Number: A85874-002 USB KB/ MS Fan -12V +12V +5V SCSI Term 5V--> 1.8V 5V--> 2.5V Super I/O VTT VRM CORE VRM NIC 1 SCSI VIDEO Processor 1 PCI Slots 5VSB --> 3.3VSB +3.3V +5VSB Power Supply CSB5 Processor 2 NIC 2 CIOB20 Sahalee DIMM HE-SL Intel® Server Board SDS2 Clock/Voltage Generation and Distribution Figure 9.
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Connections Intel® Server Board SDS2 8. Connections 8.1 Power Distribution Board Connector The main power supply connection is obtained using a 24-pin connector. A separate 8-pin connector is used for the +12 V power connector dedicated to providing power to the processor. A third 5-pin auxiliary signal connector is used to communicate with the power supply. The following tables define the pin-outs of these connectors. Table 52.
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Intel® Server Board SDS2 8.2 Connections 3 PS_ALERT (Not Used) 4 ReturnS 5 3.3RS Memory Module Connector The SDS2 Server Board has six PC-133 SDRAM DIMM connectors and supports registered SDRAM modules. For more information on DIMM modules refer to PC SDRAM Registered DIMM Design Support Document Rev 1.2. Table 55.
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Connections 8.3 Intel® Server Board SDS2 System Management Headers 8.3.1 ICMB Connector The Intelligent Chassis Management Bus (ICMB) allows inter-chassis communications between intelligent chassis. This makes it possible to externally access chassis management functions, alert logs, port-mortem data, etc. Additional information about ICMB can be found in the Intelligent Chassis Management Bus, Version 1.0. Table 56.
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Intel® Server Board SDS2 Connections Table 59. HSBP-B Connector Pin-out Pin Signal Name Description 1 IPMB_SDA 5 VSB Data Line 2 GND GND 3 IPMB_SCL 5 VSB Clock Line 4 I2C_ADR_CNTRL Address Control 8.4 Front Panel Header A 34-pin header is provided for cabling to the system front panel. The header contains reset, NMI, power control buttons, and LED indicators. The table below details the pin-outs of the header. Table 60.
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Connections 8.5 Intel® Server Board SDS2 PCI Slot Connector The Server Board support two 32-bit, 33-MHz 5V PCI Slots and four 64-bit, 66-MHz 3.3 V PCI Slots. The tables below define their pin-outs. Table 61. 32-bit 5 V PCI Slot Pin-out Pin Side B Side A Pin Side B Side A 1 -12 V TRST# 32 AD[17] AD[16] 2 TCK +12 V 33 C/BE[2]# +3.3 V 3 Ground TMS 34 Ground FRAME# 4 TDO TDI 35 IRDY# Ground 5 +5 V +5 V 36 +3.
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Intel® Server Board SDS2 Connections Pin Side B Side A Pin Side B Side A 1 -12 V TRST# 49 M66EN AD[09] 2 TCK +12 V 50 Ground Ground 3 Ground TMS 51 Ground Ground 4 TDO TDI 52 AD[08] C/BE[0]# 5 +5 V +5 V 53 AD[07] +3.3 V 6 +5 V INTA# 54 +3.3 V AD[06] 7 INTB# INTC# 55 AD[05] AD[04] 8 INTD# +5 V 56 AD[03] Ground 9 PRSNT1# RSV 57 Ground AD[02] 10 RSV +3.3 V 58 AD[01] AD[00] 11 PRSNT2# RSV 59 +3.3 V +3.
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Connections 8.6 Intel® Server Board SDS2 Pin Side B Side A Pin Side B Side A 45 AD[14] +3.3 V 91 Ground AD[32] 46 Ground AD[13] 92 RSV RSV 47 AD[12] AD[11] 93 RSV Ground 48 AD[10] Ground 94 Ground RSV I/O Connectors 8.6.1 VGA Connector The video connector interface is a standard VGA compatible 15-pin connector. An ATI RAGE XL video controller with 4 MB of on-board video memory supplies video. The following table details the pin-out of the VGA connector. Table 63.
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Intel® Server Board SDS2 Connections Connector Contact Number Signal Name Signal Name Connector Contact Number 3 +DB(14) -DB(14) 37 4 +DB(15) -DB(15) 38 5 +DB(P1) -DB(P1) 39 6 +DB(0) -DB(0) 40 7 +DB(1) -DB(1) 41 8 +DB(2) -DB(2) 42 9 +DB(3) -DB(3) 43 10 +DB(4) -DB(4) 44 11 +DB(5) -DB(5) 45 12 +DB(6) -DB(6) 46 13 +DB(7) -DB(7) 47 14 +DB(P) -DB(P) 48 15 GROUND GROUND 49 16 GROUND GROUND 50 17 RESERVED RESERVED 51 18 RESERVED RESERVED 52 19
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Connections 8.6.4 Intel® Server Board SDS2 1 TXDP 7 RXDP 2 TXDM 8 RXDM 3 N/C 9 Activity LED Cathode 4 N/C 10 Link LED Anode 5 N/C 11 Speed LED Anode 6 N/C 12 3VSB IDE Connector There is one IDE channel on the Server Board through the use of a 40-pin connector. The connector pin-out is detailed in the table below. Note IDE LED hard disk drive activity (Pin 39) signal is not routed to the front panel connector. IDE hard disk activity will not cause the front panel LED’s to turn on.
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Intel® Server Board SDS2 Connections Pin Signal Name 1 Fused 5 V 2 USB_PORT1_D- 3 USB_PORT1_D+ 4 GND 5 Fused 5 V 6 USB_PORT2_D- 7 USB_PORT2_D+ 8 GND 9 Fused 5 V 10 USB_PORT3_D- 11 USB_PORT3_D+ 12 GND A 10-pin header (2X5) located at CN18 on the Server Board provides an option to cable out the USB to the front panel. The pin-out of the header is detailed in the following table that is representative of the Foxconn HL07051-P9 Housing located at CN18.
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Connections Intel® Server Board SDS2 Table 69. 34-pin Floppy Connector Pin-out 8.6.
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Intel® Server Board SDS2 8.6.8 Connections Pin Signal Name Description 1 DCD Data Carrier Detect 2 RXD Receive Data 3 TXD Transmit Data 4 DTR Data Terminal Ready 5 GND Ground 6 DSR Data Set Ready 7 RTS Request to Send 8 CTS Clear to Send 9 RI Ring Indicate 10 KEY Key Parallel Port One DB25 parallel port connector is provided on the rear I/O. The following table details the pinout of the connector. Table 72. DB25 Parallel Port Pin-out Pin 8.6.
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Connections Intel® Server Board SDS2 Keyboard Pin 8.7 Mouse Signal Name Pin Signal Name 1 KBDATA 1 MSDATA 2 N/C 2 N/C 3 GND 3 GND 4 Fused 5V 4 Fused 5V 5 KBCLK 5 MSCLK 6 N/C 6 N/C Miscellaneous Headers 8.7.1 Fan Headers There are two fan connectors for processors and four system fan connectors. All six fans are monitored by the BMC and they all share the same pin-out. Table 74.
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Intel® Server Board SDS2 Connections Table 76. External Drive Activity Header Pin-out Pin 8.8 Signal name 1 N/C 2 DRIVE_ACTIVITY 3 DRIVE_ACTIVITY 4 N/C Rear I/O Panel The following diagram shows the locations of keyboard, mouse, USB, serial, parallel, video, and NIC connector interfaces on the system I/O panel, as viewed from the rear of the system. Figure 10. SDS2 Server Board Rear I/O Panel 8.
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Jumpers CN Numbers Intel® Server Board SDS2 Qty Manufacturer Mfg.
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Intel® Server Board SDS2 Jumpers CN42 DEFAULT FUNCTION CN48 DEFAULT FUNCTION 1 2 OPEN CLOSED = CMOS Clear 1 OPEN CLOSED = FRB3 Timer Disable 3 4 OPEN CLOSED = Password Disable 5 6 OPEN CLOSED = RSV CN49 DEFAULT FUNCTION 7 8 OPEN CLOSED = RSV 1 OPEN CLOSED = BMC Force Update 9 10 OPEN CLOSED = BIOS Recovery 11 12 CLOSED SPARE JUMPER CN50 DEFAULT FUNCTION 1 CABLED CLOSED = Chassis Instrusion Disable CN59 DEFAULT FUNCTION 1 2 OPEN CPU Frequency Select CN45
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Jumpers Intel® Server Board SDS2 CN50 FUNCTION 1 Chassis Intrusion 2 FUNCTION CN42 FUNCTION 1 2 CMOS Clear CN59 FUNCTION 1 2 CPU Frequency Select 3 4 CPU Frequency Select 5 6 CPU Frequency Select 7 8 CPU Frequency Select 9 10 RSV 11 12 RSV CN46 1 2 BIOS Write Protect 3 4 Password Disable CN47 1 2 BMC Write Protect 5 6 RSV CN48 1 2 FRB3 7 8 RSV CN49 1 2 FRC 9 10 BIOS Recovery 11 12 Spare Jumper Figure 12.
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Intel® Server Board SDS2 Jumpers The following tables describe each jumper options. Table 78. System Configuration Jumper Options Option Description CMOS Clear When CN42’s pins 1 and 2 are OPEN (default), CMOS contents are preserved through the system reset. When they are CLOSED, CMOS contents are set to manufacturing default during system reset. Password Disable When CN42’s pins 3 and 4 are OPEN (default), the current system password is maintained during a system reset.
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Jumpers Intel® Server Board SDS2 Table 80. List of Assembled Jumpers in Production 9.2 9.2.
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Intel® Server Board SDS2 Jumpers 2. Power off the system, unplug the power cord, and remove the chassis panel. 3. Add a jumper on CN42 pins 9-10 (BIOS Recovery). 4. Insert the BIOS Recovery floppy diskette into the disk drive. 5. Reinstall the chassis panel; plug in the power cord(s), and power on the system. 6. The screen will remain blank while the BIOS Recovery is performed. At the end of the BIOS Recovery, two high-pitched beeps will sound and the floppy drive access light will turn off.
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Electrical and Thermal Specifications Intel® Server Board SDS2 10. Electrical and Thermal Specifications This section describes the electrical and thermal specifications required to integrate this board in a system. 10.1 Absolute Maximum Ratings Operation of the SDS2 Server Board at conditions beyond those shown in the following table may cause permanent damage to the system (provided for stress testing only).
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Intel® Server Board SDS2 Electrical and Thermal Specifications Table 82. SDS2 Server Board Power Consumption Device(s) +3.3 V +5 V +12 V -12 V 5 V Standby Server Board 3.85 A 2.5 A 0.3 A 0.1 A 1.2 A Processors – – 6.3A – – Memory 8.3A – – – – PCI Slots 6.1A 2A 0.2A 0.1A – Fans – – 1.3A – – Peripherals – 4.7 A 4.6 A – – Total Current 18.25 A 9.2 A 12.7 A 0.2 A 1.2 A Total Total Power 60.23 W 46.0 W 152.4 W 2.4 W 6.0 W 267.0W 10.
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Electrical and Thermal Specifications 96 Intel® Server Board SDS2 Revision 1.
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Intel® Server Board SDS2 Electrical and Thermal Specifications Electrical and Thermal Specifications Intel® Server Board SDS2 10.4 Estimateded Server Board MTBF The estimated Mean-Time Between Failures (MTBF) is calculated at 103,996 hours at a maximum operating temperature Figure 13. Output Voltage Timing The table below shows the calculated numbers. Time all output voltages stay within regulation after loss of AC.
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Intel® Server Board SDS2 Mechanical Specifications 11. Mechanical Specifications The following figure shows the Server Board mechanical drawing. Figure 15. SDS2 Server Board Mechanical Drawing Revision 1.
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Regulatory and Integration Information Intel® Server Board SDS2 12. Regulatory and Integration Information 12.1 Regulatory Compliance The SDS2 server board complies with the following safety standard requirements. Table 88. Safety Regulations Regulation UL 1950/CSA950 Title Bi-National Standard for Safety of Information Technology Equipment including Electrical Business Equipment.
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Intel® Server Board SDS2 Regulatory and Integration Information UL Recognition Mark (USA/Canada) CE Mark (Europe) C-Tick Mark (Australia) GOST Mark (Russia) BSMI Mark (Taiwan) 12.2 Installation Instructions CAUTION: Follow these guidelines to meet safety and regulatory requirements when installing this board assembly. Read and adhere to these instructions and to the instructions supplied with the host computer and associated modules.
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Regulatory and Integration Information Intel® Server Board SDS2 If the host chassis, power supply, and other modules have not passed applicable EMC certification testing before integration, EMC testing must be conducted on a representative sample of the newly completed computer. 12.2.
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Intel® Server Board SDS2 12.2.5 Regulatory and Integration Information Use Only for Intended Applications This product was evaluated for use in ITE computers that will be installed in offices, schools, computer rooms and similar locations. The suitability of this product for other product categories other than ITE applications (such as medical, industrial, alarm systems, and test equipment) may require further evaluation. 12.2.
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Errata Listing Intel® Server Board SDS2 13. Errata Listing 13.1 Summary Errata Table The following tables indicate the errata and the document changes that apply to the Intel® Server Board SDS2. Intel intends to fix some of the errata in a future stepping of components, and to account for the other outstanding issues through documentation or specification changes as noted. The tables use the following notations: Fix: Intel intends to fix this erratum in a future release of the component.
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Intel® Server Board SDS2 Errata Listing 21. Fixed Fab 5 Keyboard and Mouse do not function under Microsoft* Windows* 2000 when legacy USB is enabled in BIOS setup 22. Fixed Data miscompares when using Seagate* ATA III model ST310215A hard drives 23. Fixed Fab 5 Boot to service partition via modem fails 24. Fixed Fab 5 Secondary IDE References Added To Documentation for FAB 5 25. No Fix Potential Mylex AcceleRAID 352 Adaptor Card Mechanical Interference at PCI Slot 6. 26.
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Errata Listing Intel® Server Board SDS2 13.2 Errata [DD1] 1. Intel® RAID controller SRCMR not yet supported with Intel® Server Board SDS2 Problem: The Intel RAID Controller SRCMR installed on the Intel Server Board SDS2 is currently an unsupported configuration. Intel has induced a failure condition in Intel Server Board SDS2 systems configured with the Intel RAID Controller SRCMR under extreme workloads during final validation testing.
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Intel® Server Board SDS2 Errata Listing in BIOS Setup, the following error message will appear when attempting to update the FRU/SDR files: Updating the FRU and Sensor Data Records Packaged file is corrupt Implication: If console redirection is set to enabled in BIOS Setup, the Intel Server Board SDS2 FRU/SDR files cannot be updated. Workaround: Make sure that console redirection is set to disabled in BIOS Setup (this is the default BIOS setting) before performing a FRU/SDR file update.
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Errata Listing Intel® Server Board SDS2 Server Board SDS2 does not service this interrupt when the BIOS Logo screen is enabled. Implication: When booting the Intel Server Board SDS2 with an Intel RAID Controller or ICP Vortex* RAID controller installed, the system will halt during POST when the Intel Server Board SDS2 BIOS Logo screen is enabled. Workaround: A workaround for this issue is to press the ESC key when the Intel BIOS logo screen appears.
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Intel® Server Board SDS2 Errata Listing 2. On the Utilities page, drop down the menu and choose the Platform Confidence Test option. 3. Click on the Create Diskette icon that appears and when prompted, choose to save the file to a temporary folder on your hard drive. 4. Locate the file you just saved and run the SDS2PCT.exe program obtained from the CD. This will extract the files for the Platform Confidence Test onto the floppy along with a file called MKBOOT.BAT. 5.
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Errata Listing Intel® Server Board SDS2 Problem: Microsoft* Windows* 2000 NIC driver set 5.1.2 v.5.41.27 prevents the Intel® Server Board SDS2 from making a DPC LAN connection when the operating system is loaded. Implication: NIC driver set 5.1.2 v.5.41.27 for Microsoft* Windows* 2000 should not be used with the Intel® Server Board SDS2 if DPC LAN is being used. Workaround: Intel recommends using NIC driver set 5.0.1 v.5.40.11 or driver set 5.1.3 v.5.41.32 in order to avoid this failure.
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Intel® Server Board SDS2 1600x1200 Errata Listing Not supported. Workaround: Utilize a video mode that is currently supported by the SDS2 Server Board. Status: Fixed. SDS2 BIOS Production Release 2.4 (Build 47) and later versions have added support for additional high resolution video modes. The following video modes are supported by SDS2 BIOS Production Release 2.
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Errata Listing Intel® Server Board SDS2 Implication: The SDS2 server board will not complete POST if more than 4GB or more of total system memory is installed and the Extended RAM step option in BIOS Setup is set to “Every Location”. Workaround: Choose a different option besides “Every Location” for the Advanced à Memory Configuration à Extended RAM Step BIOS Setup option. The default setting for this option is “Disabled”. Status: Fixed. This issue is fixed in SDS2 BIOS Production Release 2.
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Intel® Server Board SDS2 Errata Listing Workaround: This issue does not occur when the SDS2 onboard SCSI controller option ROM is set to “Disabled”. To disable the SDS2 onboard SCSI controller option ROM, access the Intel® Server Board SDS2 BIOS Setup by pressing F2 during POST. In BIOS Setup, change the Advanced à PCI Configuration à Embedded SCSI à Option ROM Scan option to “Disabled”. Status: Fixed. This issue is fixed in SDS2 BIOS Production Release 2.5 (Build 48) and later versions. 15.
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Errata Listing Intel® Server Board SDS2 In addition to this message, the SC5100 front panel system status LED will light solid amber, indicating a system temperature fault. This condition will continue to appear during POST each time the SDS2 system is rebooted, until AC power is removed from the system by disconnecting the AC power cord.
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Intel® Server Board SDS2 Errata Listing Implication: The SDS2 system BIOS will enter the PXE boot sequence if various numeric keys are pressed during POST. Workaround: Do not enter numeric keys during the POST process. Status: Fixed. This issue is fixed in SDS2 BIOS Production Release 2.5 (Build 48) and later versions. 19.
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Errata Listing Implication: Intel® Server Board SDS2 If you are installing the Intel Server Board SDS2 into the Intel SC5100 Server Chassis, Intel recommends installing the rubber bumper included with the server board. If you are installing the Intel Server Board SDS2 into a chassis other than the Intel SC5100 Server Chassis, compare the rubber bumper height to the chassi standoff height.
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Intel® Server Board SDS2 Errata Listing Figure 1. Placing the Rubber Bumper in the Chassis Workaround: Utilizing the rubber bumper with the SDS2 Server Board is a workaround for issues that may occur due to vibration during shipment of the integrated system product. Status: NoFix. 21.
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Errata Listing 22. Intel® Server Board SDS2 Data miscompares when using Seagate* ATA III model ST310215A hard drives Problem: Intel has induced data miscompares in SDS2 sytems configured with a Seagate* ATA III model ST310215A hard drive under extreme workloads during validation testing. Intel has verfied that other hard drive models are not affected by this issue.
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Intel® Server Board SDS2 Errata Listing Problem: Mechanical interference between the Myelex installed memory module (DIMM) and the onboard SCSI connector occurs if a Wide or Singled Ended SCSI cable is installed on embedded SCSI A or B connector. LVD SCSI cable connectors do not interfer. Implication: Mechanical interference may damage the Mylex memory module connector and DIMM when the Mylex AcceleRADI 352 Adaptor Card ins fully seated in PCI slot 6 connector.
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Errata Listing 28. Intel® Server Board SDS2 OB P100 NICs do not show at POST but attempt PXE boot and appear in Boot Menu Problem: On board NIC are not displayed during post but do appear in Boot Device menu. These controllers will also attempt to do a PXE boot if no other bootable devices are found. Implication: Not all boot devices displayed during POST when diagnostic display is enabled. Workaround: None. This is by design.
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Intel® Server Board SDS2 Status: 30. Errata Listing Will Not Fix. Can Not Change BIOS SETUP IDE Options Using Key Problem: In SETUP, when attempting to change any option under the Primary/Secondary IDE controller sub-menu, one must use the space bar. The enter key does not function. The TPS does not mention having to use the SPACE bar to change the options . Implication: Possible confusion on how to select the options in the BIOS Setup IDE sub menu. Workaround: None.
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Errata Listing Intel® Server Board SDS2 Alternatively, the updated drivers may installed using the following procedure to install NW6. . a) Boot to DOS and fdisk/format the C: partition. b) Boot to C: drive and load loddvc.com and cdex from there: "loddvc aoatapi.sys /D:cdr0m001 cdex.exe /D:cdr0m001 /L:z" (aotapi.sys is whatever driver is appropriate for the cd -- /L:z requires lastdrive=z in config.sys) c) Copy server.exe from SP1 to the nwupdate directory. d) Run "Install.
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Intel® Server Board SDS2 34. Errata Listing Peer-to-peer PCI transactions are not supported between the CIOB-controlled 64-bit PCI bus and the legacy 32-bit PCI bus controlled by the HE-SL north bridge Problem: Peer-to-peer PCI transactions are supported between the two peer CIOBcontrolled, 64-bit, 66MHz, 3.3V PCI busses. Peer-to-peer PCI transactions are not supported between the CIOB-controlled 64-bit, 66MHz, 3.
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Errata Listing Intel® Server Board SDS2 therefore does not display any text messages and does not allowing the CTRLS option. Status: Will not fix. 126 Revision 1.
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Intel® Server Board SDS2 Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) with alpha entries following (e.g., “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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Glossary Intel® Server Board SDS2 Term Definition Mux multiplexor NMI Non-maskable Interrupt OEM Original equipment manufacturer Ohm Unit of electrical resistance P32-A 32 bit PCI Segment P64-B Full Length 64/66 MHz PCI Segment P64-C Full Length 64/66 MHz PCI Segment PBGA Pin Ball Grid Array PCT Platform Confidence Test PLD programmable logic device PMI Platform management interrupt POST Power On Self Test RAM Random Access Memory ROM Read Only Memory RTC Real-time clock.
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Intel® Server Board SDS2 Reference Documents Reference Documents Refer to the following documents for additional information: Refer to the following documents for additional information: • Coppermine-T Processor Data Sheet Rev 1.0, FM-2051 • Tualatin Processor Electrical, Mechanical, and Thermal Specification Rev 0.9, FM-2024 • Tualatin Dual Processor Platform Design Guide Rev 1.0, OR2660 • ServerWorks Champion North Bridge 2.0 HE Version 1.8 • ServerWorks Champion North Bridge 2.
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Index Intel® Server Board SDS2 Index 1 1.25V, 39 12V, 39 -12V, 39 2 2.5 V logic levels, 68 2.5V, 39 29LV008B, 3, 20 2-way interleaved SDRAM, 6, 9 3 3.3 V logic levels, 68 3.3v Standby, 39 3.
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Index Intel® Server Board SDS2 D Data channels, 21 Data transfer, 8 Device ID, 11, 12 DIMM, 42 DIMM sockets, 2, 6 DMA Mode, 17 DP8473, 19 Graphics Controller, 2 H Hard reset, 30 Hecetas, 27 HE-SL CNB20 North Bridge, 2 HE-SL memory registers, 8 Host bus interface, 4 Host controller, 21 E Errata Summary Table, 103 Error handling, 34, 35 Error logging, 35 Error pins, 32 ESCD parameter block, 65 Event Logging, 39 Event, Trigger, 37 Exit Menu, 51, 54, 64 F Fan connectors, 84 Fan speed measurement, 27 Fan tac
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Intel® Server Board SDS2 Memory configuration requirements, 6 Memory controller, 2, 4, 6, 8 Memory interleaving, 6 Memory scrubbing, 6, 9 MIRQ#, 32 Missing CPU Module, 41 MPS, 57 Multiple-bit error detection, 6 Multiple-bit errors, 4 N N_KBD_PINITL, 30 N_PWRGD+00, 30 N_RST_BMCRST_L, 28, 30 N_RST_P6_PWRGOOD, 30 N844077, 19 Network Interface Controller, 2, 11 NIC connector, 85 NMI, 39 North Bridge, 2, 4, 8, 9, 11, 31 NVRAM, 65 NVRAM modification, 51 NVRAM.
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Index Intel® Server Board SDS2 SCSI Controller, 13, 68 SDRAM DIMM connectors, 73 Security, 51, 54 Processor, 45, 46 SEL Log Sensors, 38 Sensor Event, 37 Sensor Failure, 43 Sensor, Processor, 45, 46 Serial ports, 3, 18, 19, 82 Serialized IRQs, 21 SERIRQ, 21 SERR#, 32, 37, 76, 77 ServerSet* III HE-SL chipset, 2 Set NMI Source command, 37 Set SEL Time command, 43 Setup utility, 51 Setup Utility, 65 Setup utility navigation, 52 Setup utility, entering, 52 Shadow, 45, 46, 47 Single-bit error correction, 6 Sing
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Intel® Server Board SDS2 Index Zero-channel RAID controller, 14 Revision 1.