PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer’s Manual 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx 317453-005 Revision 3.
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Revision History Date Version Comments June 2008 3.8 Updated EEPROM Word 21h bit descriptions (section 5.6.18). June 2008 3.7 Updated Sections 13.4.30 and 13.4.31 (added text stating to use the Interrupt Throttling Register (ITR) instead of registers RDTR and RADV for applications requiring an interrupt moderation mechanism). Jan 2007 3.6 Added a note to sections 13.4.20 and 13.4.21 for the 82547Gi/EI. Sept 2007 3.5 Updated section 13.4.16. May 2007 3.4 Updated section 6.4.1.
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Contents Contents 1 Introduction .................................................................................................................. 1 1.1 1.2 1.3 1.4 1.5 1.6 2 Architectural Overview ............................................................................................ 7 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 Scope .................................................................................................................... 1 Overview ..........................................
Contents 3.3 3.4 3.5 3.6 4 PCI Local Bus Interface ......................................................................................... 71 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5 PCI Configuration ................................................................................................ 71 4.1.1 PCI-X Configuration Registers ........................................................... 79 4.1.2 Reserved and Undefined Addresses.................................................. 82 4.1.
Contents 5.5 5.6 5.7 7 EEUPDATE Utility ............................................................................................... 97 5.5.1 Command Line Parameters ............................................................... 97 EEPROM Address Map....................................................................................... 98 5.6.1 Ethernet Address (Words 00h-02h)..................................................103 5.6.2 Software Compatibility Word (Word 03h) ..........................
Contents 6 Power Management ............................................................................................... 129 6.1 6.2 6.3 6.4 8 Ethernet Interface .................................................................................................. 153 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 9.2 9.3 802.1q VLAN Packet Format ............................................................................ 175 9.1.1 802.1q Tagged Frames ..............................................................
Contents 10.1.3 11 Blink Control .....................................................................................180 PHY Functionality and Features ......................................................................183 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 Auto-Negotiation................................................................................................183 11.1.1 Overview ...................................................................
Contents 12 Dual Port Characteristics .................................................................................... 203 12.1 12.2 12.3 12.4 12.5 13 Register Descriptions........................................................................................... 211 13.1 13.2 13.3 13.4 x Introduction ....................................................................................................... 203 Features of Each MAC......................................................................
Contents 13.5 13.6 13.7 13.4.25 Receive Descriptor Base Address Low ............................................302 13.4.26 Receive Descriptor Base Address High ...........................................302 13.4.27 Receive Descriptor Length ...............................................................303 13.4.28 Receive Descriptor Head .................................................................303 13.4.29 Receive Descriptor Tail ..................................................................
Contents 13.8 xii 13.7.10 Collision Count ................................................................................. 341 13.7.11 Defer Count ...................................................................................... 342 13.7.12 Transmit with No CRS...................................................................... 342 13.7.13 Sequence Error Count...................................................................... 343 13.7.14 Carrier Extension Error Count ..........................
Contents 13.8.5 13.8.6 13.8.7 13.8.8 13.8.9 13.8.10 13.8.11 14 General Initialization and Reset Operation ..................................................371 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 15 Receive Data FIFO Packet Count ....................................................366 Transmit Data FIFO Head Register..................................................366 Transmit Data FIFO Tail Register ....................................................367 Transmit Data FIFO Head Saved Register ..
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Introduction Introduction 1.1 1 Scope This document serves as a software developer’s manual for 82546GB/EB, 82545GM/EM, 82544GC/EI, 82541(PI/GI/EI), 82541ER, 82547GI/EI, and 82540EP/EM Gigabit Ethernet Controllers. Throughout this manual references are made to the PCI/PCI-X Family of Gigabit Ethernet Controllers or Ethernet controllers. Unless specifically noted, these references apply to all the Ethernet controllers listed above. 1.
Introduction For the 82544GC/EI, when connected to an appropriate SerDes, it can alternatively provide an Ethernet interface for 1000 Base-SX or LX applications (IEEE 802.3z). Note: The 82546EB/82545EM is SerDes PICMG 2.16 compliant. The 82546GB/82545GM is SerDes PICMG 3.1 compliant. 82546GB/EB Ethernet controllers also provide features in an integrated dual-port solution comprised of two distinct MAC/PHY instances.
Introduction • IEEE 802.3x compliant flow control support — Enables control of the transmission of Pause packets through software or hardware triggering — Provides indications of receive FIFO status • State-of-the-art internal transceiver (PHY) with DSP architecture implementation — Digital adaptive equalization and crosstalk — Echo and crosstalk cancellation — Automatic MDI/MDI-X crossover at all speeds and compensation for cable length — Media Independent Interfaces (MII) IEEE 802.
Introduction 1.3.5 Additional Performance Features • Provides adaptive Inter Frame Spacing (IFS) capability, enabling collision reduction in half duplex networks (82544GC/EI) • Programmable host memory receive buffers (256 B to 16 KB) • Programmable cache line size from 16 B to 128 B for efficient usage of PCI bandwidth • Implements a total of 64 KB (40 KB for the 82547GI/EI) of configurable receive and transmit data FIFOs.
Introduction 1.3.6 Manageability Features (Not Applicable to the 82544GC/EI or 82541ER) • Manageability support for ASF 1.0 and AoL 2.0 by way of SMBus 2.0 interface and either: — TCO mode SMBus-based management packet transmit / receive support — Internal ASF-compliant TCO controller 1.3.
Introduction 1.4 Conventions This document uses notes that call attention to important comments: Note: 1.4.1 Indicates details about the hardware’s operations that are not immediately obvious. Read these notes to get information about exceptions, unusual situations, and additional explanations of some PCI/PCI-X Family of Gigabit Ethernet Controller features. Register and Bit References This document refers to Ethernet controller register names using all capital letters.
Architectural Overview Architectural Overview 2.1 2 Introduction This section provides an overview of the PCI/PCI-X Family of Gigabit Ethernet Controllers. The following sections give detailed information about the Ethernet controller’s functionality, register description, and initialization sequence. All major interfaces of the Ethernet controllers are described in detail. The following principles shaped the design of the PCI/PCI-X Family of Gigabit Ethernet Controllers: 1.
Architectural Overview 2.2 External Architecture Figure 2-1 shows the external interfaces to the 82546GB/EB.
Architectural Overview Figure 2-3 shows the external interfaces to the 82547GI/EI.
Architectural Overview 2.3 Microarchitecture Compared to its predecessors, the PCI/PCI-X Family of Gigabit Ethernet Controller’s MAC adds improved receive-packet filtering to support SMBus-based manageability, as well as the ability to transmit SMBus-based manageability packets. In addition, an ASF-compliant TCO controller is integrated into the controller’s MAC for reduced-cost basic ASF manageability. Note: The 82544GC/EI and 82541ER do not support SMBus-based manageability.
Architectural Overview When the Ethernet controller serves as a PCI target, it follows the PCI configuration specification, which allows all accesses to it to be automatically mapped into free memory and I/O space at initialization of the PCI system. When processing transmit and receive frames, the Ethernet controller operates as master on the PCI bus.
Architectural Overview • Offloading the receiving and transmitting IP and TCP/UDP checksums • Directly retransmitting from the transmit FIFO any transmissions resulting in errors (collision detection, data underrun), thus eliminating the need to re-access this data from host memory 2.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks The controller’s CSMA/CD unit handles all the IEEE 802.
Architectural Overview Note: Refer to the Extended Device Control Register (bits 23:22) for mode selection (see Section 13.4.6). The link can be configured by several methods. Software can force the link setting to AutoNegotiation by setting either the MAC in TBI mode (internal SerDes for the 82546GB/EB and 82545GM/EM), or the PHY in internal PHY mode.
Architectural Overview 2.3.8 FLASH Memory Interface The Ethernet controller provides an external parallel interface to a FLASH device. Accesses to the FLASH are controlled by the Ethernet controller and are accessible to software as normal PCI reads or writes to the FLASH memory mapping area. The Ethernet controller supports FLASH devices with up to 512 KB of memory. Note: 2.4 The 82540EP/EM provides an external interface to a serial FLASH or Boot EEPROM device. See Appendix B for more information.
Architectural Overview 2.5 Ethernet Addressing Several registers store Ethernet addresses in the Ethernet controller. Two 32-bit registers make up the address: one is called “high”, and the other is called “low”. For example, the Receive Address Register is comprised of Receive Address High (RAH) and Receive Address Low (RAL). The least significant bit of the least significant byte of the address stored in the register (for example, bit 0 of RAL) is the multicast bit.
Architectural Overview 2.6 Interrupts The Ethernet controller provides a complete set of interrupts that allow for efficient software management. The interrupt structure is designed to accomplish the following: • Make accesses “thread-safe” by using ‘set’ and ‘clear-on-read’ rather than ‘read-modify-write’ operations. • Minimize the number of interrupts needed relative to work accomplished. • Minimize the processing overhead associated with each interrupt.
Architectural Overview 2.7 Hardware Acceleration Capability The Ethernet controller provides the ability to offload IP, TCP, and UDP checksum for transmit. The functionality provided by these features can significantly reduce processor utilization by shifting the burden of the functions from the driver to the hardware. The checksum offloading feature is briefly outlined in the following sections. More detail about all of the hardware acceleration capabilities is provided in Section 3.2.9. 2.7.
Architectural Overview Descriptors store the following information about the buffers: • The physical address • The length • Status and command information about the referenced buffer Descriptors contain an end-of-packet field that indicates the last buffer for a packet. Descriptors also contain packet-specific information indicating the type of packet, and specific operations to perform in the context of transmitting a packet, such as those for VLAN or checksum offload.
Receive and Transmit Description Receive and Transmit Description 3.1 3 Introduction This section describes the packet reception, packet transmission, transmit descriptor ring structure, TCP segmentation, and transmit checksum offloading for the PCI/PCI-X Family of Gigabit Ethernet Controllers. Note: 3.2 The 82544GC/EI does not support IPv6.
Receive and Transmit Description If manageability is enabled and if RCMCP is enabled then ARP request packets can be directed over the SMBus or processed internally by the ASF controller rather than delivered to host memory (not applicable to the 82544GC/EI or 82541ER. 3.2.2 Receive Data Storage Memory buffers pointed to by descriptors store packet data.
Receive and Transmit Description layers. The packet checksum is always reported in the first descriptor (even in the case of multidescriptor packets). Upon receipt of a packet for Ethernet controllers, hardware stores the packet data into the indicated buffer and writes the length, Packet Checksum, status, errors, and status fields. Length covers the data written to a receive buffer including CRC bytes (if any).
Receive and Transmit Description Receive Descriptor Status Bits Note: 3.2.3.2 Description TCPCS (bit 5) TCP Checksum Calculated on Packet When Ignore Checksum Indication is deasserted (IXSM = 0b), TCPCS bit indicates whether the hardware performed the TCP/UDP checksum on the received packet. 0b = Do not perform TCP/UDP checksum; 1b = Perform TCP/UDP checksum Pass/Fail information regarding the checksum is indicated in the error bit (TCPE) of the descriptor receive errors (RDESC.ERRORS).
Receive and Transmit Description Table 3-3. Receive Errors (RDESC.ERRORS) Layout 7 6 5 4 3 2 1 0 RXE IPE TCPE RSV CXEa RSV SEQ RSVb SE RSVb CE a. 82544GC/EI only. b. 82541xx, 82547GI/EI, and 82540EP/EM only. Receive Descriptor Error bits Description RXE (bit 7) RX Data Error Indicates that a data error occurred during the packet reception. A data error in TBIa mode (82544GC/EI)/internal SerDes (82546GB/EB and 82545GM/EM) refers to the reception of a /V/ code (see Section 8.2.1.3).
Receive and Transmit Description Receive Descriptor Error bits Description SEQ (bit 2) Sequence Error When set, indicates a received packet with a bad delimiter sequence (in TBI mode/ internal SerDes). In other 802.3 implementations, this would be classified as a framing error. A valid delimiter sequence consists of: idle →start-of-frame (SOF) → data, →pad (optional) → end-of-frame (EOF) → fill (optional) → idle. SE (bit 1) Symbol Error When set, indicates a packet received with bad symbol.
Receive and Transmit Description 3.2.4 Receive Descriptor Fetching The descriptor fetching strategy is designed to support large bursts across the PCI bus. This is made possible by using 64 on-chip receive descriptors and an optimized fetching algorithm. The fetching algorithm attempts to make the best use of PCI bandwidth by fetching a cache line (or more) descriptors with each burst. The following paragraphs briefly describe the descriptor fetch algorithm and the software control provided.
Receive and Transmit Description 3.2.5 Receive Descriptor Write-Back Processors have cache line sizes that are larger than the receive descriptor size (16 bytes). Consequently, writing back descriptor information for each received packet would cause expensive partial cache line updates. Two mechanisms minimize the occurrence of partial line write backs: • Receive descriptor packing • Null descriptor padding The following sections explain these mechanisms. 3.2.5.
Receive and Transmit Description The receive descriptor head and tail pointers reference 16-byte blocks of memory. Shaded boxes in the figure represent descriptors that have stored incoming packets but have not yet been recognized by software. Software can determine if a receive buffer is valid by reading descriptors in memory rather than by I/O reads. Any descriptor with a non-zero status byte has been processed by the hardware, and is ready to be handled by the software.
Receive and Transmit Description • Receive Descriptor Tail register (RDT) This register holds a value that is an offset from the base, and identifies the location beyond the last descriptor hardware can process. Note that tail should still point to an area in the descriptor ring (somewhere between RDBA and RDBA + RDLEN). This is because tail points to the location where software writes the first new descriptor.
Receive and Transmit Description Initial State Idle Packet received & transferred to host memory Restart Count Other receive timer interrupt Restart Count Running Generate Int Packet received & transferred to host memory Timer expires Figure 3-3. Packet Delay Timer Operation (State Diagram) 3.2.7.1.2 Receive Interrupt Absolute Delay Timer (RADV) The Absolute Timer ensures that a receive interrupt is generated at some predefined interval after the first packet is received.
Receive and Transmit Description The diagrams below show how the Packet Timer and Absolute Timer can be used together: C ase A: U sing only an absolute tim er A bsolute Tim er Value Interrupt generated due to PKT #1 PKT #1 PKT #2 PKT #3 PKT #4 C ase B: U sing an absolute tim e in conjunction w ith the Packet tim er A bsolute Tim er Value A bsolute Tim er Value PKT #1 PKT #2 PKT #3 PKT #4 PKT #5 PKT #6 1) Packet tim er expires 2) Interrupt generated 3) Absolute tim er reset ... ... ...
Receive and Transmit Description 3.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT) The minimum descriptor threshold helps avoid descriptor under-run by generating an interrupt when the number of free descriptors becomes equal to the minimum amount defined in RCTL.RDMTS (measured as a fraction of the receive descriptor ring size). 3.2.7.4 Receiver FIFO Overrun FIFO overrun occurs when hardware attempts to write a byte to a full FIFO.
Receive and Transmit Description The Packet checksum is the one’s complement over the receive packet, starting from the byte indicated by RXCSUM.PCSS (0b corresponds to the first byte of the packet), after stripping. For example, for an Ethernet II frame encapsulated as an 802.3ac VLAN packet and with RXCSUM.PCSS set to 14 decimal, the Packet Checksum would include the entire encapsulated frame, excluding the 14-byte Ethernet header (DA,SA,Type/Length) and the 4-byte q-tag.
Receive and Transmit Description Table 3-5. Supported Receive Checksum Capabilities HW IP Checksum Calculation Packet Type HW TCP/UDP Checksum Calculation IPv4 Packet has IP options (IP header is longer than 20 bytes) Yes Yes Packet has TCP or UDP options Yes Yes IP header’s protocol field contains a protocol # other than TCP or UDP. Yes No a. The IPv6 header portion can include supported extension headers as described in the IPv6 Filter section. b.
Receive and Transmit Description 3.2.9.2 SNAP/VLAN Filter This filter checks the next headers looking for an IP header. It is capable of decoding Ethernet II, Ethernet SNAP, and IEEE 802.3ac headers. It skips past any of these intermediate headers and looks for the IP header. The receive configuration settings determine which next headers are accepted. See the various receive control configuration registers such as RCTL (RCTL.VFE), VET, and VFTA. 3.2.9.
Receive and Transmit Description • The protocol stack calculates the number of packets required to transmit this block based on the MTU size of the media and required packet headers. • For each packet of the data block: — Ethernet, IP and TCP/UDP headers are prepared by the stack. — The stack interfaces with the software device driver and commands the driver to send the individual packet. — The driver gets the frame and interfaces with the hardware.
Receive and Transmit Description Table 3-7. Transmit Descriptor (TDESC) Layout 63 30 0 28 24 23 20 19 0 Buffer Address [63:0] 8 3.3.3 29 NR DEXT NR DTYP NR Legacy Transmit Descriptor Format To select legacy mode operation, bit 29 (TDESC.DEXT) should be set to 0b. In this case, the descriptor format is defined as shown in Table 3-8. The address and length must be supplied by software. Bits in the command byte are optional, as are the Checksum Offset (CSO), and Checksum Start (CSS) fields.
Receive and Transmit Description Transmit Descriptor Legacy Notes: Description CMD Command field See Section 3.3.3.1 for a detailed field description. STA Status field See Section 3.3.3.2 for a detailed field description. RSV Reserved Should be written with 0b for future compatibility. CSS Checksum Start Field The Checksum start field (TDESC.CSS) indicates where to begin computing the checksum.
Receive and Transmit Description 3.3.3.1 Transmit Descriptor Command Field Format The CMD byte stores the applicable command and has fields shown in Table 3-10. Table 3-10. Transmit Command (TDESC.CMD) Layout 7 6 5 4 3 2 1 0 IDE VLE DEXT RSV RPSa RS IC IFCS EOP a. 82544GC/EI only. TDESC.CMD 38 Description IDE (bit 7) Interrupt Delay Enable When set, activates the transmit interrupt delay timer.
Receive and Transmit Description TDESC.CMD Notes: IC (bit 2) Insert Checksum When set, the Ethernet controller needs to insert a checksum at the offset indicated by the CSO field. The checksum calculations are performed for the entire packet starting at the byte indicated by the CCS field. IC is ignored if CSO and CCS are out of the packet range. This occurs when (CSS ≥ length) OR (CSO ≥ length - 1). IC is valid only when EOP is set.
Receive and Transmit Description TDESC.STATUS Note: 3.3.4 Description TU RSV (bit 3) Transmit Underrun Indicates a transmit underrun event occurred. Transmit Underrun might occur if Early Transmits are enabled (based on ETT.Txthreshold value) and the 82544GC/EI was not able to complete the early transmission of the packet due to lack of data in the packet buffer. This does not necessarily mean the packet failed to be eventually transmitted. The packet is successfully re-transmitted if the TCTL.
Receive and Transmit Description 3.3.5 TCP/IP Context Transmit Descriptor Format The TCP/IP context transmit descriptor provides access to the enhanced checksum offload facility available in the Ethernet controller. This feature allows TCP and UDP packet types to be handled more efficiently by performing additional work in hardware, thus reducing the software overhead associated with preparing these packets for transmission.
Receive and Transmit Description 3.3.6 TCP/IP Context Descriptor Layout The following section describes the layout of the TCP/IP context transmit descriptor. To select this descriptor format, bit 29 (TDESC.DEXT) must be set to 1b and TDESC.DTYP must be set to 0000b. In this case, the descriptor format is defined as shown in Table 3-13. Note that the TCP/IP context descriptor does not transfer any packet data. It merely prepares the checksum hardware for the TCP/IP Data descriptors that follow.
Receive and Transmit Description Table 3-14. Transmit Descriptor (TDESC) Layout Transmit Descriptor Offload Description TUCSE TCP/UDP Checksum Ending Defines the ending byte for the TCP/UDP checksum offload feature. Setting TUCSE field to 0b indicates that the checksum covers from TUCCS to the end of the packet. TUCSO TCP/UDP Checksum Offset Defines the offset where to insert the TCP/UDP checksum field in the packet data buffer.
Receive and Transmit Description Transmit Descriptor Offload Notes: RSV Reserved Should be programmed to 0b for future compatibility. STA TCP/UDP Status field Provides transmit status indication. Section 3.3.6.2 provides the bit definition for the TDESC.STA field. TUCMD TCP/UDP command field The command field provides options that control the checksum offloading, along with some of the generic descriptor processing functions. Section 3.3.6.1 provides the bit definitions for the TDESC.TUCMD field.
Receive and Transmit Description Table 3-15. Command Field (TDESC.TUCMD) Layout 7 6 5 4 3 2 1 0 IDE RSV DEXT RSV RS TSE IP TCP TDESC.TUCMD Description IDE (bit 7) Interrupt Delay Enable IDE activates the transmit interrupt delay timer. Hardware loads a countdown register when it writes back a transmit descriptor that has the RS bit and the IDE bit set. The value loaded comes from the IDV field of the Interrupt Delay (TIDV) register. When the count reaches 0, a transmit interrupt occurs.
Receive and Transmit Description 3.3.6.2 TCP/UDP Offload Transmit Descriptor Status Field Four bits are reserved to provide transmit status, although only one is currently assigned for this specific descriptor type. The status word is only written back to host memory in cases where the RS is set in the command. Table 3-16. Transmit Status Layout 3 2 1 RSV TDESC.STA 3.3.7 0 DD Description RSV Reserved Reserved for future use. Reads as 0b.
Receive and Transmit Description Table 3-17. Transmit Descriptor (TDESC) Layout – (Type = 0001b) 0 Address [63:0] 8 0 Special 63 POPTS 48 47 RSV STA DCMD 40 39 36 35 32 31 Transmit Descriptor DTYP DTALEN 24 23 20 19 0 Description Address Data buffer address Address of the data buffer in the host memory which contains a portion of the transmit packet. DTALEN Data Length Field Total length of the data pointed to by this descriptor, in bytes.
Receive and Transmit Description 3.3.7.1 TCP/IP Data Descriptor Command Field The Command field provides options that control checksum offloading and TCP segmentation features along with some of the generic descriptor processing features. Table 3-18. Command Field (TDESC.DCMD) Layout 7 6 5 4 3 2 1 0 IDE VLE DEXT RSV RPSa RS TSE IFCS EOP a. 82544GC/EI only. TDESC.DCMD 48 Description IDE (bit 7) Interrupt Delay Enable When set, activates the transmit interrupt delay timer.
Receive and Transmit Description TDESC.DCMD Description TSE (bit 2) TCP Segmentation Enable TSE indicates that this descriptor is part of the current TCP Segmentation context. If this bit is not set, the descriptor is part of the “normal” context. IFCS (Bit 1) Insert IFCS Controls the insertion of the FCS/CRC field in normal Ethernet packets. IFCS is only valid in the last descriptor of the given packet (qualified by the EOP bit).
Receive and Transmit Description TDESC.STA 3.3.7.3 Description LC (bit2) Late Collision Indicates that late collision occurred while working in half-duplex mode. It has no meaning while working in full-duplex mode. Note that the collision window is speed dependent: 64 bytes for 10/100 Mb/s and 512 bytes for 1000 Mb/s operation. EC (bit 1) Excess Collision Indicates that the packet has experienced more than the maximum excessive collisions as defined by TCTL.CT control field and was not transmitted.
Receive and Transmit Description When CTRL.VME is set to 1b, all packets transmitted from the Ethernet controller that has VLE set in the DCMD field is sent with an 802.1Q header added to the packet. The contents of the header come from the transmit descriptor special field and from the VLAN type register. The special field is ignored if the VLE bit in the transmit descriptor command field is 0b. The special field is valid only when EOP is set. Table 3-21. Special Field (TDESC.
Receive and Transmit Description Circular Buffer Base Head Owned By Hardware Transmit Queue Tail Base + Size Figure 3-4. Transmit Descriptor Ring Structure Shaded boxes in Figure 3-4 represent descriptors that have been transmitted but not yet reclaimed by software. Reclaiming involves freeing up buffers associated with the descriptors.
Receive and Transmit Description Once activated, hardware fetches the descriptor indicated by the hardware head register. The hardware tail register points one beyond the last valid descriptor. Software can determine if a packet has been sent by setting the RS bit (or the RPS bit for the 82544GC/EI only) in the transmit descriptor command field. Checking the transmit descriptor DD bit in memory eliminates a potential race condition.
Receive and Transmit Description Since the benefit of delaying and then bursting transmit descriptor write-backs is small at best, it is likely that the threshold are left at the default value (0b) to force immediate write-back of transmit descriptors and to preserve backward compatibility. Descriptors are written back in one of three conditions: • TXDCTL.WTHRESH = 0b and a descriptor which has RS1 set is ready to be written back • Transmit Interrupt Delay timer expires • TXDCTL.WTHRESH > 0b and TXDCTL.
Receive and Transmit Description • Link status change (LSC) - Set when the link status changes. When using the internal PHY, link status changes are determined and indicated by the PHY via a change in its LINK indication. When using an external TBI device (82544GC/EI only), the device might indicate a link status change using its LOS (loss of sync) indication.
Receive and Transmit Description 3.5.1 Assumptions The following assumption applies to the TCP Segmentation implementation in the Ethernet controller: • The RS bit operation is not changed. Interrupts are set after data in buffers pointed to by individual descriptors is transferred to hardware. • Checksums are not accurate above a 12 K frame size.
Receive and Transmit Description 3.5.2.1 TCP Segmentation Data Fetch Control To perform TCP Segmentation in the Ethernet controller, the DMA unit must ensure that the entire payload of the segmented packet fits into the available space in the on-chip Packet Buffer. The segmentation process is performed without interruption. The DMA performs various comparisons between the payload and the Packet Buffer to ensure that no interruptions occur.
Receive and Transmit Description • TCP with options • UDP with limitations. UDP (unlike TCP) is not a “reliable protocol”, and fragmentation is not supported at the UDP level. UDP messages that are larger than the MTU size of the given network medium are normally fragmented at the IP layer. This is different from TCP, where large TCP messages can be fragmented at either the IP or TCP layers depending on the software implementation.
Receive and Transmit Description • IPv4 Header — Length should be set to zero — Identification Field should be set as appropriate for first packet of send (if not already) — Header Checksum should be zeroed out unless some adjustment is needed by the driver • IPv6 Header — Length should be set to zero • TCP Header — Sequence Number should be set as appropriate for first packet of send (if not already) — PSH, and FIN flags should be set as appropriate for last packet of send — TCP Checksum should be set t
Receive and Transmit Description Note: 3.5.7 It is recommended that the entire header section, as described by the TCP Context Descriptor HDRLEN field, be coalesced into a single buffer and described using a single data descriptor. IP and TCP/UDP Headers This section outlines the format and content for the IP, TCP and UDP headers. The Ethernet controller requires baseline information from the software device driver in order to construct the appropriate header information during the segmentation process.
Receive and Transmit Description Byte 3 Byte 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Total length LSB Byte 1 7 6 5 4 3 2 1 0 TYPE of service MSB R N M E F F S Fragment Offset Low Byte 0 Fragment Offset High Version IP Hdr Length Identification LSB Header Checksum 7 6 5 4 3 2 1 0 Layer 4 Protocol ID MSB Time to Live Source Address Destination Address Options Figure 3-9. IPv4 Header (Little-Endian Order) Flags Field Definition: The Flags field is defined below.
Receive and Transmit Description The TCP header is first shown in the traditional (RFC 793) representation. Because byte and bit ordering is confusing in that representation, the TCP header is also shown in little-endian format. The actual data is fetched from memory in little-endian format.
Receive and Transmit Description TCP Length = Payload + HDRLEN - TUCSS “Payload” is normally MSS except for the last packet where it represents the remainder of the payload. 0 31 IP Source Address IP Destination Address Zero Layer 4 Protocol ID TCP Length Figure 3-13. TCP Pseudo Header Content (Traditional Representation) IP Source Address IP Destination Address Upper Layer Packet Length Zero Next Header Figure 3-14.
Receive and Transmit Description UDP pseudo header has the same format as the TCP pseudo header. The IPv4 pseudo header conceptually prefixed to the UDP header contains the IPv4 source address, the IPv4 destination address, the IPv4 protocol field, and the UDP length (same as the TCP Length discussed above). The IPv6 pseudo header for UDP is the same as the IPv6 pseudo header for TCP. This checksum procedure is the same as is used in TCP.
Receive and Transmit Description Three specific types of checksum are supported by the hardware in the context of the TCP Segmentation offload feature: • IPv4 checksum (IPv6 does not have a checksum) • TCP checksum • UDP checksum Each packet that is sent via the TCP segmentation offload feature optionally includes the IPv4 checksum and either the TCP or UDP checksum. All checksum calculations use a 16-bit wide one’s complement checksum. The checksum word is calculated on the outgoing data.
Receive and Transmit Description PCI FIFO IP/TCP Header Header Update Checksum Calculation Packet Data Packet Data TX Packet FIFO Packet Data HOST Memory IP/TCP Header Buf f er TCP Segmentation Data Flow Header processing Descriptors f etch Header processing Data Fetch Pause IP/TCP Header Packet Data Fetch Checksum Header Prototy pe f etch Insertion Checksum Calculations Data Fetch resume Data Fetch Pause Checksum Header Insertion Checksum Calculations Time Ev ents Scheduling Figure 3-19
Receive and Transmit Description 3.5.9.1 TCP/IP/UDP Header for the First Frame The hardware makes the following changes to the headers of the first packet that is derived from each TCP segmentation context. • IPv4 Header — IP Total Length = MSS + HDRLEN – IPCSS — IP Checksum — IPv6 Header — Payload Length = MSS + HDRLEN - IPCSS • TCP Header — Sequence Number: The value is the Sequence Number of the first TCP byte in this frame. — If FIN flag = 1b, it is cleared in the first frame.
Receive and Transmit Description 3.5.9.
Receive and Transmit Description Three fields in the TCP/IP Context Descriptor set the context of the IP checksum offloading feature: • IPCSS This field specifies the byte offset form the start of the transferred data to the first byte to be included in the checksum. Setting this value to 0b means that the first byte of the data is included in the checksum. The maximum value for this field is 255. This is adequate for typical applications.
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PCI Local Bus Interface 4 PCI Local Bus Interface The PCI/PCI-X Family of Gigabit Ethernet Controllers are PCI 2.2 or 2.3 compliant devices and implement the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0. Note: 4.1 The 82540EP/EM, 82541xx, and 82547GI/EI do not support PCI-X mode. PCI Configuration The PCI Specification requires implementation of PCI Configuration registers.
PCI Local Bus Interface 1Ch Base Address 3 (unused) 20h Base Address 4 (unused) 2h4 Base Address 5 (unused) 28h Cardbus CIS Pointer (not used) 2Ch Subsystem ID 30h 34h Reserved 38h 3Ch a. Subsystem Vendor ID Expansion ROM Base Address Cap_Ptr Reserved Max_Latency (00h) Min_Grant (FFh) Interrupt Pin (01h) Interrupt Line Refer to Table 4-2.
PCI Local Bus Interface Cache Line Size1 Used to store the cache line size. The value is in units of 4 bytes. A system with a cache line size of 64 bytes sets the value of this register to 10h. The only sizes that are supported are 16, 32, 64, and 128 bytes. All other sizes are treated as 0b. See the information about exceptions in Section 4.4. Unsupported values affect PCI cache line support.
PCI Local Bus Interface All base address registers have the following fields: Field Mem Bit(s) 0 Read/ Write R Initial Value 0b for mem Description 0b indicates memory space. 1b indicates I/O. 1b for I/O Type 2:1 R 00b for 32bit Indicates the address space size. 10b for 64bit 10b = 64-bit 00b = 32-bit 0b = non-prefetchable space Prefetch 3 R 0b 1b = prefetchable space Ethernet controller implements non-prefetchable space since it has read side-effects.
PCI Local Bus Interface Expansion ROM Base Address This register is used to define the address and size information for boottime access to the optional Flash memory. 31 11 10 Expansion Rom Base Address Bit(s) Read/ Write En 0 R/W 0b Reserved 10:1 R 0b Field 1 0 Reserved Initial Value En Description 1b = Enables expansion ROM access. 0b = Disables expansion ROM access. Always read as 0b. Writes are ignored. The lower bits of the address are hard-wired to 0b.
PCI Local Bus Interface Field Read/ Write Bit(s) Initial Value Description Indicates the address space where the CIS is located. 0 = Configuration Space 1 = BAR0 2 = BAR1 Space 2:0 R/W 0 or 2 3 = BAR2 4 = BAR3 5 = BAR4 6 = BAR5 7 = Expansion ROM Offset Subsystem ID 31:3 R 0 or 4 Offset within the specified address space, multiplied by eight. When enabled, the value indicates that the CIS (Card Information Structure) is at an offset of 4*8, or 32 bytes into the Flash memory.
PCI Local Bus Interface Max_Lat/Min_Gnt1 The Ethernet controller places a very high load on the PCI bus during peak transmit and receive traffic. In full duplex mode, it has a peak throughput demand of 250 MB/sec. The peak delivered bandwidth on a 64-bit PCI bus at 33 MHz is 264 MB/sec, so the bus is fully saturated when transmit and receive are operating simultaneously.
PCI Local Bus Interface Bit(s) Initial Value 4 0b Memory Write and Invalidate Enable (not applicable to the 82547GI/EI). 5 0b Palette Snoop Enable. 6 0b Parity Error Response (not applicable to the 82547GI/EI). 7 0b Wait Cycle Enable. 8 0b SERR# Enable (not applicable to the 82547GI/EI). 9 0b Fast Back-to-Back Enable. 10a 0b Interrupt Disable (INTA# or CSA signaled). 0b Reserved. 15:10 15:11a a. Description 82541xx and 82547GI/EI only. Table 4-4.
PCI Local Bus Interface a. 4.1.1 Bit(s) Initial Value Description 12 0b Received Target Abort. 13 0b Received Master Abort. 14 0b Signaled System Error (not applicable to the 82547GI/EI). 15 0b Detected Parity Error (not applicable to the 82547GI/EI). 82541xx and 82547GI/EI only. PCI-X Configuration Registers The Ethernet controller supports additional configuration registers that are specific to PCI-X.
PCI Local Bus Interface 4.1.1.3 PCI-X Command 15 7 Read Write 4 3 Max. Split Transactions Reserved Bits 6 Initial Value 2 Read Count 1 0 RO DP Description 0 RW 0b Data Parity Error Recovery Enable. If this bit is 1b, the Ethernet controller attempts to recover from Parity errors. If this bit is 0b, the Ethernet controller asserts SERR# (if enabled) whenever the Master Data Parity Error bit (Status Register, bit 8) is set. 1 RW 1b Enable Relaxed Ordering.
PCI Local Bus Interface 4.1.1.4 PCI-X Status 31 29 28 26 25 23 22 21 20 19 18 17 16 Res. Read Size Max. Split Rd Byte Cplx USC SCD 133 64b Read/ Write Bits Intial Value 15 8 Bus Number 7 3 Device Number 2 0 Func. Num. Description 2:0 R 0b Function Number. This number forms part of the Requester and Completer IDs for PCI-X transactions. 7:3 R 1Fh Device Number. The system assigns a device number (other than 0b) to the Ethernet controller.
PCI Local Bus Interface Read/ Write Bits Intial Value Description Designed Maximum Outstanding Split Transactions. A 0b indicates that the Ethernet controller is designed to have at the most one outstanding transaction. Register 25:23 R 0b Maximum Outstanding Transactions 0 1 1 2 2 3 3 4 4 8 5 12 6 16 7 32 Designed Maximum Cumulative Read Size. Indicates a number that is greater or equal maximum cumulative outstanding bytes to be read at one time.
PCI Local Bus Interface Message Signaled Interrupts1 4.1.3 Message Signaled Interrupt (MSI) capability is optional for PCI 2.2 or 2.3, but required for PCI-X. When Message Signaled Interrupts are enabled, instead of asserting an interrupt pin, the Ethernet controller generates an interrupt using a memory write command. The address and most of the data of the command are determined by the system and programmed in configuration registers.
PCI Local Bus Interface 4.1.3.1.3 Message Control 15 8 Reserved Read/ Write Bits 0 R 7 64b 6 Multiple Enable Initial Value 0b 4 3 1 Multiple Capable 0 En Description MSI Enable. If 1b, Message Signaled Interruptsa are enabled and the Ethernet controller generates Message Signaled Interrupts instead of asserting INTA#. Multiple Message Capable. Indicates the number of messages requested. The Ethernet controller only requests one message. Register 3:1 a.
PCI Local Bus Interface 4.1.3.1.4 Message Address Read/ Write Bits 31:0 4.1.3.1.5 RW Description Message Address – Written by the system to indicate the lower 32bits of the address to use for the MSI memory write transaction. The lower two bits are always written as 0b. 0b Message Upper Address Read/ Write Bits 31:0 4.1.3.1.6 RW Initial Value Description Message Upper Address – Written by the system to indicate the upper 32-bits of the address to use for the MSI memory write transaction.
PCI Local Bus Interface Table 4-5. PCI and PCI-X Encoding Difference C/BE Encoding PCI Commands Abr. PCI-X Commands Abr. Dh Dual Address Cycle DAC Dual Address Cycle DAC Eh Memory Read Line MRL Memory Read Block MRB Fh Memory Write & Invalidate MWI Memory Write Block MWB As a target, the Ethernet controller only accepts transactions that address its BARs or a configuration transaction in which its IDSEL input is asserted.
PCI Local Bus Interface Following are a few specific rules: • For descriptor fetches, the burst length is always equal to the multiple of cache line sizes set by the transmit and receive descriptor fetch threshold fields. (See Section 3.2.4 and Section 3.4.1) For descriptor writes, the transfer size ranges from 8 bytes to N cache line's worth of data. Cache line sizes are: 16, 32, 64, and 128 bytes.
PCI Local Bus Interface IDLE Wr_Req || (Cnt_Rmn != 0) Write Command Determination Aligned && (Count >= CLS) MWI Burst* !Aligned || (Aligned && (Count < CLS)) || !MWI_Enable MW Burst Cnt_Rmn = 0 Cnt_Rmn = 0 Terminate Transaction Boundary || Terminate MWI_Enable && d && Cnt_Rmn >= CLS) Terminate MWI Boundary Evaluation !MWI_Enable || (!Aligned || Cnt_Rmn < CLS) * Either the initiation or continuation of the MWI Burst Count = Amount of data for XFR Cnt_Rmn = Remaining data for XFR Wr_Req = Initial
PCI Local Bus Interface 4.3.1.2 MW Bursts • The Ethernet controller always continues the burst until the end. If the system is concerned about MWI usage, it disconnects at the cache line boundary. The Ethernet controller then restarts the transaction and re-evaluates command usage. Note: 4.3.2 The algorithm described above defaults to the MW case when the MWI enable bit in the Configuration Register is set to 0b.
PCI Local Bus Interface Outstanding Memory Read When the Ethernet controller masters a memory read and is responded to with a split response it waits for the completion of the data as a target. The Ethernet controller allows one outstanding memory read command at any time. The Ethernet controller continues to master posted memory writes and split completions if there are any. Relaxed Ordering • The Ethernet controller takes advantage of the relaxed ordering rules in PCI-X.
PCI Local Bus Interface 4.4.1 Target Transaction Termination When the Ethernet controller accepts a transaction as a target it always disconnects the transaction after a single data phase by following the “Master Completion Termination” in PCI 2.2, 2.3, or “Single data phase disconnect termination” in PCI-X. The “memory” in the Ethernet controller is actually a set of registers and is marked as “non-prefetchable”. This is also the case for FLASH memory. 4.
PCI Local Bus Interface 4.7 CardBus Application (82541PI/GI/EI Only) The 82541PI/GI/EI has some features to facilitate its use in a CardBus application, following revision 7 of the PC Card specification. To use the 82541PI/GI/EI on CardBus, an external flash memory is required. Configure the Base Address Registers to 32-bit (required for CardBus) and enable CLKRUN in EEPROM. Setting these bits also enables the CardBus Information Space (CIS) pointer in the PCI Configuration Space.
EEPROM Interface EEPROM Interface 5.1 5 General Overview The PCI/PCI-X Family of Gigabit Ethernet Controllers uses an EEPROM device for storing product configuration information. The EEPROM is divided into four general regions: • Hardware accessed – loaded by the Ethernet controller after power-up, PCI Reset deassertion, D3->D0 transition, or software commanded EEPROM reset (CTRL_EXT.EE_RST).
EEPROM Interface 5.2 Component Identification Via Programming Interface Ethernet controller stepping is identified by the following register contents. Table 5-1.
EEPROM Interface Table 5-1. Component Identification Stepping Note: 5.3 Vendor ID Device ID Description 82541GI-B1 8086h 1076h Cooper 82541GI-B1 8086h 1077h Mobile 82541PI-C0 8086h 1076h Cooper 82541ER-C0 8086h 1078h Cooper 82540EP-A 8086h 1017 Desktop 82540EP-A 8086h 1016 Mobile 82540EM-A 8086h 100E Desktop 82540EM-A 8086h 1015 Mobile These Ethernet controllers also provide identification data through the Test Access Port (TAP).
EEPROM Interface The EEPROM interface trace routing is not critical because the interface runs at a very slow speed. Note: 5.3.1 For the 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI, the EEPROM access algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write cycles. the extra pulses might violate the timing specifications of some EEPROM devices. In selecting a serial EEPROM, choose a device that specifies “don’t care” shift clock states between accesses.
EEPROM Interface In ASF Mode1, the Ethernet controller's ASF function reads the ASF CRC word to determine if the EEPROM is valid. If the CRC is not valid, the ASF Configuration registers retain their default value. This CRC does not affect any of the remaining Ethernet controller's configuration, including the Management Control Register. 5.5 EEUPDATE Utility The EEUPDATE utility meets the two basic requirements for an in-circuit programming utility.
EEPROM Interface EEPROM Address Map1 5.6 Table 5-2 lists the EEPROM address map for the Ethernet controllers. Each word listed is described in the sections that follow. Note: The “LAN A/B” column in Table 5-2 is only applicable to the 82546GB/EB. Table 5-2.
EEPROM Interface Table 5-2.
EEPROM Interface Table 5-2.
EEPROM Interface Table 5-2.
EEPROM Interface Table 5-3.
EEPROM Interface 5.6.1 Ethernet Address (Words 00h-02h) The Ethernet Individual Address (IA) is a six-byte field that must be unique for each Ethernet port (and unique for each copy of the EEPROM image). The first three bytes are vendor specific. The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). For a MAC address of 12-34-56-78-90-AB, words 2:0 load as follows (note that these words are byteswapped): Word 0 = 3412 Word 1 = 7856 Word 2 - AB90 Note: 5.6.
EEPROM Interface Table 5-4. Software Compatibility Word (Word 03h) 3 Reserved Reserved for future use. Set this bit to 0b. 2 BOB PCI bridge. Set this bit to 0b (default) to disable PCI bridge; set to 1b to enable PCI bridge. 1b is the default setting for the 82540EP/EM. 1:0 a. 5.6.3 Reserved Reserved for future use. Set these bits to 0b. Not applicable to the 82544GC/EI or 82541ER.
EEPROM Interface 5.6.7 Initialization Control Word 1 (Word 0Ah) The first word read by the Ethernet controller contains initialization values that: • Sets defaults for some internal registers • Enables/disables specific features • Determines which PCI configuration space values are loaded from the EEPROM Table 5-5.
EEPROM Interface Table 5-5. Initialization Control Word 1 (Word 0Ah) 82541xx and 82547GI/EI Only Internal VREG Power Down Control 7 This bit is used to define the usage of the internal 1.2 V dc and 1.8 V dc regulators to supply power. 0b = Yes (default). 1b = No (external regulators used). Note: Reserved bit for all other Ethernet controllers. Bit Name Description 6:5 Reserved Reserved for future use. Set these bits to 0b. 4 Reserved Reserved for copper PHY. Set this bit to 0b.
EEPROM Interface 5.6.10 Device ID (Word 0Dh, 11h1) If the signature bits (15:14) and bit 1 (Load Subsystem IDs) of word 0Ah are valid, this word is read in to initialize the Subsystem ID. For the 82546GB, the Device ID must be forced to 107Bh for SerDes-SerDes interface operation. For the 82545GM, the Device ID should be 1028h. This ensures proper functionality with Intel drivers and boot agent. Note: 5.6.
EEPROM Interface Table 5-6. Initialization Control Word 2 (Word 0Fh) Bit Name Description 82541PI/GI Only. 0b = MAC runs at full speed. 8 MAC Clock Speed 1b = MAC runs at 1/4 speed on any drop from 1000 Mb/s. Note: Reserved bit for all other Ethernet controllers (set to 0b). Formally FLASH Disable, now located in Initialization Control Word 3, bit 3. When set to 0b (default), enables Message Signalled Interrupts (MSI) in standard PCI mode.
EEPROM Interface 5.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh) These settings are specific to individual platform configurations for the 82541xx and 82547GI/EI and should not be altered from the reference design unless instructed to do so. Future Intel Ethernet controllers might use this space differently. 5.6.
EEPROM Interface Table 5-8. Software Defined Pins Control (Word 10h, 20h) Bit Name Description SDP7(3) Pin - Initial Direction. SDPDIR[7] 15 SDPDIR[3] for the 82541xx and 82547GI/EI Set this bit to 0b (default) to configure the initial hardware value of the SDP7(3)_IODIR bit in the Extended Device Control Register (CTRL_EXT) following power up. Set this bit to 1b if not connected on a board or if used as an output. SDP6(2) Pin - Initial Direction.
EEPROM Interface Table 5-8. Software Defined Pins Control (Word 10h, 20h) Bit 2 Name Description D3COLD_WAKEUP_ADV_EN Set this bit to 1b (default) to configure the initial hardware default value of the ADVD3WUC bit in the Device Control Register (CTRL) following power up. Set this bit to 0b to not configure the initial hardware default value of the ADVD3WUC bit in the Device Control Register (CTRL) following power up. SDP1 Pin - Initial Output Value.
EEPROM Interface 5.6.19 Circuit Control (Word 21h) This word is loaded into the Circuit Control Register (CIRC) for setting PCI-X driver strength. See Table 5-2 and Table 5-3 for suggested values. Note: 5.6.20 PCI-X is not applicable to the 82540EP/EM, 82541xx, and 82547GI/EI.
EEPROM Interface 5.6.24 Management Control (Word 13h1, 23h2) The following table lists the initial settings for the Management Control Register as well as valid bits for the IPv4 Address and the IPv6 Address. Table 5-10. Initial Management Control Register Settings Bit Name Description This bit controls the initial value of the MANC.RSP_EN bit. 15 Enable ARP Response Filtering 0b: ARP response packets are delivered to host memory. 14 Reserved Reserved. Set this bit to 0b.
EEPROM Interface Table 5-10. Initial Management Control Register Settings Bit Name Description This bit is controlled by the ASF agent. Manually set this bit for TCO mode. 2 Reset on Force TCO Reset the Ethernet controller on a ForceTCO SMBus Command with the “Force” bit set to 1b (default) in TCO mode, or on various conditions in ASF mode. Set this bit to 0b if the SMBus is disabled. This bit is controlled by the ASF agent. 1 ASF Mode Set this bit to 1b to enable ASF mode.
EEPROM Interface 5.6.26 Initialization Control 3 (Word 14h1 high byte, 24h high byte) This word controls the general initialization values. Table 5-12. Initialization Control 3 Bit 7:5 Name Reserved Description Reserved. Set these bits to 0b. Controls the value advertised in the Interrupt Pin field of the PCI Configuration header for this device/function.
EEPROM Interface 5.6.27 IPv4 Address (Words 15h - 16h1 and 25h - 26h) The following table lists the initial values for the IPv4 addresses. Table 5-13. IPv4 Addresses Bit Name Description The initial value of IPv4 Address Table entry 0. (IP4AT[0]). 31:0 Note: 5.6.28 IPv4 Address Refer to the EEPROM Address Map listed in Table 5-2 for an indication of how the bytes are stored.
EEPROM Interface Table 5-15. Boot Agent Main Setup Options Bit Name Description PXE Presence. Setting this bit to 0b Indicates that the image in the FLASH contains a PXE image. Setting this bit to 1b indicates that no PXE image is contained. 15 PPB The default for this bit is 0b in order to be backwards compatible with existing systems already in the field. If this bit is set to 0b, EEPROM word 32h (PXE Version) is valid.
EEPROM Interface Table 5-15. Boot Agent Main Setup Options Bit Name Description Default Boot Selection. These bits select which device is the default boot device. These bits are only used if the agent detects that the BIOS does not support boot order selection or if the MODE field of word 31h is set to MODE_LEGACY. 4:3 DBS 00b = Network boot, then local boot 01b = Local boot, then network boot 10b = Network boot only 11b = Local boot only 2 BBS BIOS Boot Specification (OBSOLETE).
EEPROM Interface . Table 5-16. Boot Agent Configuration Customization Options (Word 31h) Bit Name Description 15:14 SIG Signature. These bits must be set to 1b to indicate that this word has been programmed by the agent or other configuration software. 13:11 Reserved Reserved for future use. Set these bits to 0b. Selects the agent's boot order setup mode.
EEPROM Interface Table 5-16. Boot Agent Configuration Customization Options (Word 31h) Bit Name Description Disable Protocol Select. 2 DPS If set to 1b, no changes to the boot protocol is allowed. The default for this bit is 0b; allow changes to the boot protocol. Disable Title Message. 1 If set to 1b, the title message displaying the version of the boot agent is suppressed; the Control-S message is also suppressed.
EEPROM Interface 5.6.33 IBA Capabilities (Word 33h) Word 33h is used to enumerate the boot technologies that have been programmed into the FLASH. It is updated by IBA configuration tools and is not updated or read by IBA. Table 5-18. IBA Capabilities Bit Name Description 15:14 SIG Signature. These bits must be set to 1b to indicate that this word has been programmed by the agent or other configuration software. 13:5 Reserved Reserved for future use. Set these bits to 0b.
EEPROM Interface 5.6.35 Checksum Word Calculation (Word 3Fh) The Checksum word (3Fh) should be calculated such that after adding all the words (00h-3Fh), including the Checksum word itself, the sum should be BABAh. The initial value in the 16-bit summing register should be 0000h and the carry bit should be ignored after each addition. This checksum is not accessed by the Ethernet controller. If CRC checking is required, it must be performed by software. Note: 5.6.
EEPROM Interface 5.7 Parallel FLASH Memory All Ethernet controllers except the 82540EP/EM provide an external parallel interface to an optional FLASH or boot EEPROM device. Accesses to the FLASH memory are controlled by the Ethernet controllers, but are accessible to host software as normal PCI reads or writes to the FLASH memory mapping range. Software developers can also map FLASH memory to I/O space.
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FLASH Memory Interface 7 FLASH Memory Interface All Ethernet controllers (except the 82540EP/EM) provide an external parallel interface to a FLASH, or boot ROM, device such as the Atmel AT49LV0101. All accesses to this device are managed by the Ethernet controller and are accessible to software as normal PCI reads or writes to the FLASH memory mapping range. The Ethernet controller supports parallel FLASH devices with up to 4 Mb (512 KB) of memory.
FLASH Memory Interface 7.2.1 Read Accesses Upon reads to the FLASH address space, the Ethernet controller uses the TRDY# signal to insert target wait states until valid data can be read from the FLASH device and presented on the data lines. When TRDY# is asserted, the Ethernet controller drives valid data on the data lines. The processor master can then complete normal data read cycle by asserting IRDY# when it is ready.
FLASH Memory Interface CLK 1 2 3 7 8 9 10 11 12 13 14 FRAME# AD CBE# ADDRESS DATA MEM-W R BE#s IRDY# TRDY# DEVSEL# STOP# Figure 7-2.
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Power Management Power Management 6.1 6 Introduction to Power Management The PCI/PCI-X Family of Gigabit Ethernet Controllers support the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). This section describes how Power Management is implemented in the Ethernet controllers. Note: The 82541ER does not support ACPI or APM wakeup.
Power Management 6.3 D3cold support If the AUX pin is connected to logic 1b, the Ethernet controller advertises D3cold Wakeup support. The amount of power required for this function (which includes the entire Ethernet port circuitry) is advertised in the Power Management Data Register which is loaded from the EEPROM.
Power Management 6.3.1.1 Dr State At initial boot-up, once LAN_PWR_GOOD is asserted, the Ethernet controller reads the EEPROM. If the APM Mode bit in the EEPROM’s Initialization Control Word 2 is set then APM Wakeup is enabled. The system may maintain RST# asserted for an arbitrary time. During this time, and for up to 1 ms afterwards, the Ethernet controller does not assert any PCI signals except PME#. During operation, the system may assert RST# at any time.
Power Management 6.3.1.3 D0a (D0 active) Once memory space is enabled, all internal clocks are activated, the Ethernet controller enters an active state, and can then transmit and receive packets if properly configured by the software driver. The controller also signals the PHY (if using the internal PHY) to indicate full speed/ power1. If APM Wakeup was activated it remains active.
Power Management 6.3.2.1 Power Up (Off to Dr to D0u to D0a) 3RZHU 1 LAN_POWER_GOOD CLK# 5 4 RST# 8 9 Memory Access 2 Reading EEPROM Read EEPROM Read EEPROM 7 PCI Pins Running Wakeup Enabled 3:5B67$7(> @ 3 E APM Wakeup 6 APM Wakeup E LI ZDNHXS LV GLVDEOHG E LI ZDNHXS LV HQDEOHG E *& (, 2QO\ DState Dr D0u D0a Figure 6-2. Startup Timing Diagram # Notes 1 LAN_PWR_GOOD must not be asserted until all power supplies are good and the clock is stable.
Power Management 6.3.2.2 Transition From D0a to D3 and Back Without PCI Reset ,B3&,B&/. 567 ' :ULWH 0HPRU\ $FFHVV (QDEOH 5HDGLQJ ((3520 5HDG ((3520 ' ZULWH 3&, 3LQV 5XQQLQJ :DNHXS (QDEOHG $Q\ PRGH $30 RQO\ 3:5B67$7(> @ *& (, 2QO\ '6WDWH E ' D E LI ZDNHXS LV GLVDEOHG E LI ZDNHXS LV HQDEOHG E E ' E ' X ' Figure 6-3.
Power Management 6.3.2.3 Transition From D0a to D3 and Back with PCI Reset &/. 567 0HPRU\ $FFHVV (QDEOH 5HDGLQJ ((3520 5HDG ((3520 ' ZULWH 3&, 3LQV 5XQQLQJ :DNHXS (QDEOHG $Q\ PRGH $30 :DNHXS 3:5B67$7(> @ E E LI ZDNHXS LV GLVDEOHG E LI ZDNHXS LV HQDEOHG E E E *& (, 2QO\ '6WDWH ' D ' 'U ' X ' D Figure 6-4.
Power Management 6.3.2.4 PCI Reset Without Transition to D3 CLK# 3 1 RST# 7 4 Memory Access Enable 8 2 Reading EEPROM Read EEPROM 5 PCI Pins Running Wakeup Enabled Running Any mode APM Wakeup 6 PWR_STATE[1:0] *& (, 2QO\ DState E E LI ZDNHXS LV GLVDEOHG E LI ZDNHXS LV HQDEOHG D0a E E D0u Dr E D0a Figure 6-5. PCI Reset Sequence Diagram # Notes PCI-Xa 1 In 66 MHz or modes, the system must assert RST# before stopping the PCI clock.
Power Management 6.3.3 PCI Power Management Registers Power Management registers are part of the capabilities linked list pointed to by the Capabilities Pointer (Cap_Ptr) in the PCI configuration space. Refer to Section 4.1. All fields are reset by LAN_PWR_GOOD. All of the fields except PME_En and PME_Status are reset by the deassertion (rising edge) of RST#. If AUX_POWER = 0b, the PME_En and PME_Status fields also reset by the deassertion (rising edge) of RST#.
Power Management 6.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO) Bits Default R/W Description PME_Support – This 5-bit field indicates the power states in which the function may assert PME#a. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state.
Power Management 6.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO) Bits Default 0b (see description) 15 R/W Read/ Write 1b to clear 00b 14:13 01b if Manageability is enabled 0000b PME_Status – This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. The Ethernet controller returns a value of 1b for this bit if a Wakeup condition has been detected. Writing a 1b clears this bit and deasserts PME#a.
Power Management 6.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO) This register indicates support for PCI bridge specific functions. Note that these functions are not implemented in the Ethernet controller and the values are set to 00h. 6.3.3.6 Data Register 1 Byte Offset = 7 (RO) Bits 07:00 Default 00h (loaded from EEPROM) R/W Read Only Description Data returned. See the following explanation. This register is used to report power consumption and heat dissipation.
Power Management If power management is not disabled and when the Data_Select field is programmed to 0 or 4, the Ethernet controller sets the Data Register to the D0 Power value in the EEPROM. When the Data_Select field is programmed to 3 or 7, the Ethernet controller sets the Data Register to the D3 Power value in the EEPROM. Otherwise it returns 0b. 6.
Power Management • Maintains the first magic packet received in the Wakeup Packet Memory (WPM) until the driver writes a 0b to the Magic Packet Received MAG bit in the Wakeup Status Register (WUS). “APM Wakeup” is supported in all power states and only disabled if a subsequent EEPROM read results in the APM Wakeup bit being cleared or software explicitly writes a 0b to the APM Wakeup (APM) bit of the WUC register. 6.4.
Power Management After receiving a wakeup packet, the Ethernet controller ignores any subsequent wakeup packets until the driver clears all of the “Received” bits in the Wakeup Status Register (WUS). It also ignores link change events until the driver clears the Link Status Changed (LNKC) bit in the Wakeup Status Register (WUSR). 6.4.
Power Management The Ethernet controller generates a wakeup event after receiving any packet whose destination address matches one of the 16 valid programmed Receive Addresses if the Directed Exact Wakeup Enable bit is set in the Wakeup Filter Control Register (WUFC.EX). # of bytes Offset 0 6 6.4.3.1.
Power Management # of bytes Offset Field Value Action 0 6 Destination Address Compare 6 6 Source Address Skip 12a 8 Possible LLC/SNAP Header Skip 12a 4 Possible VLAN Tag Skip 12a 4 Type any 6 Synchronizing Stream FF*6+ Compare any+6 96 16 copies of Node Address A*16 Compare a. Comment MAC Header – processed by main address filter Skip Compared to Receive Address Register 0 (RAH0, RAL0) Not applicable to the 82541PI/GI/EI and 82547GI/EI.
Power Management ARP/IPv4 Request Packet1 6.4.3.1.5 The Ethernet controller supports receiving ARP Request packets for wakeup if the ARP bit is set in the Wakeup Filter Control Register (WUFC). Four IPv4 addresses are supported which are programmed in the IPv4 Address Table (IPv4AT)2. A successfully matched packet must contain a broadcast MAC address, a Protocol Type of 0806h, an ARP OPCODE of 01h, and one of the four programmed IPv4 addresses.
Power Management 6.4.3.1.6 Directed IPv4 Packet1 The Ethernet controller supports receiving Directed IPv42 packets for wakeup if the IPv4 bit is set in the WakeUp Filter Control Register (WUFC). Four IPv4 addresses are supported which are programmed in the IPv4 Address Table (IPv4AT). A successfully matched packet must contain the station’s MAC address, a Protocol Type of 0800h, and one of the four programmed IPv4 addresses.
Power Management 6.4.3.2 Directed IPv6 Packet1 The Ethernet controller supports receiving Directed IPv6 packets for wakeup if the IPv6 bit is set in the Wakeup Filter Control Register (WUFC). One IPv6 address is supported and it is programmed in the IPv6 Address Table (IPv6AT). A successfully matched packet must contain the station’s MAC address, a Protocol Type of 0800h, and the programmed IPv6 address.
Power Management 6.4.3.3 Flexible Filter The Ethernet controller supports a total of four flexible filters. Each filter is configured to recognize any arbitrary pattern within the first 128 bytes of the packet. To configure the flexible filter, the software driver must mask values into the Flexible Filter Mask Table (FFMT), the required values into the Flexible Filter Value Table (FFVT), and the minimum packet length into the Flexible Filter Length Table (FFLT).
Power Management 6.4.3.3.2 Directed IPX Packet Example A valid Directed IPX Packet contains the station’s MAC address, a Protocol Type of 8137h, and an IPX Node Address that equals to the station’s MAC address. It can include LLC/SNAP Headers and VLAN Tags. Since filtering this packet relies on the flexible filters, which use offsets specified by the OS directly, the OS must account for the extra offset LLC/SNAP Headers and VLAN tags.
Power Management Offset 18+D+S 6.4.3.5 # of Bytes 2 Field Value Action Payload Length - Check Comment Ignore 20+D+S 1 Next Header 3Ah, 00h, 2Bh, or 3Ch 21+D+S 1 Hop Limit FFh Check 22+D+S 16 Source IP Address - Ignore 38+D+S 16 Destination IP Address ICMP, or IPv6 next headers: + routing (2Bh) + dest options (3Ch) + hop-by-hop (00h) Ignore 54+D+S N Possible IPv6 Next Headers - Check Process headers to get next header.
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Ethernet Interface 8 Ethernet Interface 8.1 Introduction The PCI/PCI-X Family of Gigabit Ethernet Controllers provide a complete CSMA/CD function supporting IEEE 802.3 (10Mb/s), 802.3u (100Mb/s), 802.3z and 802.3ab (1000Mb/s) implementations. They perform all of the functions required for transmission, reception and collision handling called out in the standards.
Ethernet Interface 8.2.1 Internal SerDes Interface/TBI Mode– 1Gb/s1 The 82546GB/EB and 82545GM/EM Ethernet controllers contain one or two internal SerDes devices (depending whether or not they support one or two ports). The MAC communicates with the SerDes over a TBI interface. Normally, this interface is not exposed externally. For the 82554GC/EI, TBI mode is selectable via an external pin TBI-MODE. Software cannot override this pin.
Ethernet Interface 8.2.1.3 Code Groups and Ordered Sets Code group and ordered set definitions are defined in clause 36 of the IEEE 802.3z standard. These represent special symbols used in the encapsulation of Gigabit Ethernet packets. Table 8-1 lists a brief description of defined ordered sets for informational purposes only. Table 8-1. Code Group and Ordered Set Usage Code 8.2.
Ethernet Interface 8.2.3 MII – 10/100 Mb/s The internal MII implementation for the Ethernet controller provides full IEEE 802.3 and IEEE 802.3u compliant operation for 10Mb/s and 100Mb/s operation in conjunction with the onboard MII compliant PHY. The MII uses a clocked, nibble-wide (4-bit) data path in each direction. The clock rate for Fast Ethernet operation is 25 MHz with data transfer speed of 4 bits x 25 MHz = 100 Mb/s. For 10 Mb/s operation the clock rate is 2.
Ethernet Interface Configuration of the duplex operation of the Ethernet controller can be forced or determined via the Auto-Negotiation process. See Section 8.6 for details on link configuration setup and resolution. 8.4.1 Full Duplex All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full duplex operation.
Ethernet Interface For receives, the Ethernet controller supports carrier extended packets and packets generated during packet bursting operations (see Section 8.4.2.1 and Section 8.4.2.2). The Ethernet controller can be configured to transmit in packet burst mode via the TCTL.PBE bit in the Transmit Control register (see Section 13.4.46). Carrier extension is only defined in the IEEE 802.3z standard for half-duplex operation for operation frequencies above 100 Mb/s (Gigabit Ethernet). 8.4.2.
Ethernet Interface The normal rules for IPG are followed during packet bursting after the first packet has met the minimum slot time requirements, with the exception that the Inter Frame Content (IFC) is extension symbols rather than IDLEs. Under some circumstances, it might be desirable to extend this IPG time during a burst. This can be done via the AIFS field in the AIT register. See Section 13.4.35. 8.
Ethernet Interface The following section describes the link configuration process in the Internal Serdes for the 82546GB/EB and 82545GM/EM (TBI mode for the 82544GC/EI) and internal PHY modes. 8.6.1 Link Configuration in Internal Serdes/TBI Mode1 Internal Serdes for the 82546GB/EB and 82545GM/EM (TBI for the 82544GC/EI) Mode link configuration can be performed via the on-chip PCS function in the Ethernet controller.
Ethernet Interface A set of registers is provided to facilitate either hardware or software Auto-Negotiation. The hardware supports both hardware and software Auto-Negotiation methods for determining link configuration as well as allowing for manual configuration to force the link. The IEEE 802.
Ethernet Interface Figure 8-3. 802.3z Advertised Base Page Mapping Table 8-2. Bits Content in TXCW.txConfigWord Bit Description Np Next Page Indication When set indicates a request for next page exchange AS Asymmetric Pause Connection is Desired When set, results in independent enabling/disabling of the flow control receive and transmit.
Ethernet Interface 8.6.1.5 Forcing Link In cases where the Ethernet controller is connected to a non-Auto-Negotiating link partner, the hardware allows for manual configuration of the link via the Device Control register (CTRL). Forcing link can be accomplished by software writing a 1b to CTRL.SLU which forces the TBI PCS logic into a link up state if the LOS input is not asserted. Setting the SLU bit enables the MAC to communicate with the internal SerDes and allows recognition of the LOS signal.
Ethernet Interface Once PHY Auto-Negotiation is complete, the PHY asserts the link indication signal. Software MUST set the “set link up” bit in the Device Control Register (CTRL.SLU) before the Ethernet controller recognizes the link. Setting the SLU bit permits the MAC to recognize the LINK signal from the PHY, which indicates the PHY has gotten the link up, and to receive and transmit data. 8.6.2.
Ethernet Interface STATUS.ASDV [9:8], provides the results of speed status indication for diagnostics purposes regardless of whether the Auto-Speed Detection feature is enabled. This function is initiated with a write to the CTRL_EXT.ASDCHK bit. See Section 13.4.6 for details. 8.6.2.2.3 Automatic Detection of Link Speed using SPD-IND With the CTRL register configure as CTRL.FRCSPD = 0, the speed is reconfigured automatically each time a new linkup event is detected.
Ethernet Interface 8.6.3 Internal SerDes Mode1 Control Bit Resolution Tables 8-3, 8-4, and 8-52 list how on-chip Auto-Negotiation affects control bits in the Ethernet controller. Table 8-5 lists the case where software Auto-Negotiation is not performed and link is forced. Table 8-3. Internal Serdes Mode1 – Hardware Enabled TXCW.ANE = 1b Control Bit Effect on Control Bits CTRL.FD Ignored; duplex is set by priority resolution of TXCW and RXCW CTRL.
Ethernet Interface Table 8-5. Internal Serdes Mode1 – Auto-Negotiation Skipped TXCW.ANE = 0b Control Bit CTRL.FD Duplex is set by software for the desired mode of operation CTRL.SLU Set by software CTRL.RFCE Set by software for the desired mode of operation CTRL.TFCE Set by software for the desired mode of operation CTRL.SPEED No impact; speed always 1000 Mb/s in Internal SerDesa mode STATUS.FD Reflects the value of CTRL.FD STATUS.LU Reflects CTRL.SLU and internal link indication STATUS.
Ethernet Interface Table 8-7. GMII/MII Mode – Auto-Speed Detection CTRL.FRCSPD = CTRL.FRCDPLX = 0b; CTRL.ASDE = 1b Control Bit Effect on Control Bits CTRL.FD Duplex is set per internal duplex indication after link up assertion by PHY. CTRL.SLU Software should set to allow PHY to control. CTRL.RFCE Must be set by software after reading flow control resolution from MII registers. CTRL.TFCE Must be set by software after reading flow control resolution from MII registers. CTRL.
Ethernet Interface Table 8-9. GMII/MII Mode – Force Link CTRL.FRCSPD = CTRL.FRCDPLX = CTRL.SLU = 1b Control Bit 8.6.5 Effect on Control Bits CTRL.FD Set by software. CTRL.SLU Set by software, and assumed PHY is also forced to assert link. CTRL.RFCE Set by software for the desired mode of operation. CTRL.TFCE Set by software for the desired mode of operation. CTRL.SPEED Set by software. STATUS.FD Reflects the value of CTRL.FD. STATUS.LU Reflects CTRL.SLU set and internal link status.
Ethernet Interface 8.7 10/100 Mb/s Specific Performance Enhancements 8.7.1 Adaptive IFS1 The Ethernet controller supports back-to-back transmit Inter-Frame-Spacing (IFS) of 960 ns in 100 Mb/s operation and 9.6 µs in 10 Mb/s operation. Although back-to-back transmission is normally desirable, sometimes it can actually hurt performance in half-duplex environments due to excessive collisions.
Ethernet Interface 8.7.2 Flow Control Flow control as defined in IEEE specification 802.3x, as well as the specific operation of asymmetrical flow control defined by 802.3z, are supported. The following registers are defined for the implementation of flow control: Table 8-10.
Ethernet Interface The final check for a valid PAUSE frame is the MAC Control Opcode. At this time only the PAUSE control frame opcode is defined. It has a value of 0001h. Frame based flow control differentiates XOFF from XON based on the value of the PAUSE timer field. Non-zero values constitute XOFF frames while a value of zero constitutes an XON frame. Values in the timer field are in units of slot time. A “slot time” is hard wired to 64 byte times, or 512 ns.
Ethernet Interface Flow control capability must be negotiated between link partners via the Auto-Negotiation process. The Auto-Negotiation process can modify the value of these bits based on the resolved capability between the local device and the link partner.
Ethernet Interface The contents of the Flow Control Receive Threshold High register (FCRTH) determine at what point hardware transmits a PAUSE frame. Hardware monitors the fullness of the receive FIFO and compares it with the contents of FCRTH. When the threshold is reached, hardware sends a PAUSE frame with its pause time field equal to FCTTV. Once the receive buffer fullness reaches the low water mark, hardware sends an XON message (a PAUSE frame with a timer value of 0b).
802.1q VLAN Support 9 802.1q VLAN Support The PCI/PCI-X Family of Gigabit Ethernet Controllers provide several specific mechanisms to support 802.1q VLANs: • Optional adding (for transmits) and stripping (for receives) of IEEE 802.1q VLAN tags • Optional ability to filter packets belonging to certain 802.1q VLANs Note: 9.1 The 82541ER Ethernet controller does not support VLAN tags. 802.1q VLAN Packet Format Table 9-1 compares the format of an untagged 802.3 Ethernet packet with an 802.
802.1q VLAN Support Table 9-2. 802.1q Tagged Frames Octet 1 UP 9.2 Octet 2 CFI VID Transmitting and Receiving 802.1q Packets Since the 802.1q tag is only four bytes, adding and stripping of tags can done completely in software. (For transmits, software inserts the tag into packet data before it builds the transmit descriptor list, and for receives, software strips the four byte tag from the packet data before delivering the packet to upper layer software.
802.1q VLAN Support In summary, the 4096 bit vector is composed of 128 32-bit registers. Matching to this bit vector follows the same algorithm as indicated in Section 13.5.1 for Multicast Address filtering. The VLAN Identifier (VID) field consists of 12 bits. The upper 7 bits of this field are decoded to determine the 32-bit register in the VLAN Filter Table Array to address and the lower 5 bits determine which of the 32 bits in the register to evaluate for matching.
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Configurable LED Outputs 10 Configurable LED Outputs 10.1 Configurable LED Outputs1 The PCI/PCI-X Family of Gigabit Ethernet Controller’s MAC implements four output drivers intended for driving external LED circuits. Each MAC’s four LED outputs can be individually configured to select the particular event, state, or activity that is indicated on that output. In addition, each LED can be individually configured for output polarity as well as for blinking vs. non-blinking (steady-state) indication.
Configurable LED Outputs LED outputs can be based on the following expressions: • • • • • • • • • • • • • LINK_UP is asserted while link of any speed is maintained LINK_10 indicates link at 10 Mbps LINK_100 indicates link at 100 Mbps LINK_1000 indicates link at 1000 Mbps LINK_100/1000 indicates link at either 100 or 1000 Mbps LINK_10/1000 indicates link at either 10 or 1000 Mbps ACTIVITY is asserted when link is established and packets are being transmitted or received LINK/ACTIVITY is asserted when link
Configurable LED Outputs Note: It is especially important to note with respect to the blink-control circuit that: • the blink circuit, when enabled, exists as the LAST stage of the LED circuitry, after any (optional) signal inversion • the blink sequence occurs when the circuit input is asserted low As a result, it is possible to select combinations of IVRT and BLINK which do not make sense or produce unexpected results, such as examples previously noted.
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PHY Functionality and Features PHY Functionality and Features 11.1 11 Auto-Negotiation Auto-Negotiation between the PCI/PCI-X Family of Gigabit Ethernet Controllers and its link partner is performed by the PHY. Under normal, expected operating conditions, the MAC automatically establishes common speed and duplex settings via the PHY. This section details PHY configuration features involved in the auto-negotiation process. 11.1.
PHY Functionality and Features 11.1.2 Next Page Exchanges If 1000BASE-T mode is advertised, then the Ethernet controller PHY automatically sends the appropriate next pages to advertise the capability and negotiate master/slave mode of operation. If a developer does not want to transmit additional next pages, the next page bit (PCI-Config Register bit 15) can be set to 0b and the software need take no further action.
PHY Functionality and Features 11.1.4 Status Once the PHY completes auto-negotiation, it updates the various statuses in the PHY Status Register, Link Partner Ability Register (Base Page), Auto-Negotiation Expansion Register, and 1000BASE-T Status Register. For 1000BASE-T operation, the Auto-Negotiation Expansion Register and the Link Partner Ability Register (Base Page) are updated.
PHY Functionality and Features 11.2.1 Polarity Correction (copper only) The Ethernet controller PHY automatically corrects for polarity errors on the receive pairs in 1000BASE-T and 10BASE-T modes. In 100BASE-TX mode, the polarity does not matter. In 1000BASE-T mode, receive polarity errors are automatically corrected based on the sequence of the symbols. Once the descrambler is locked, the polarity is also locked on all pairs. The polarity becomes unlocked only when the receiver loses lock. 11.2.
PHY Functionality and Features 11.3 Cable Length Detection (copper only) In 100/1000 Mbps operation, the Ethernet controller PHY attempts to indicate the approximate length of the CAT 5 cable attached. The estimated cable length is reported as one of the following ranges: • • • • • <= 50 m 50 – 80 m 80 – 110 m 110 – 140 m >= 140 m The estimated cable length can be obtained by reading the PHY Specific Status Register bits 9:7. 11.
PHY Functionality and Features 11.4.2 D3 State, No Link Required (copper only) Each time the MAC transitions to a D3 or D0u power-state with no link required (wakeup disabled and no manageability enabled), the PHY enters its IEEE power-down mode, consuming the least amount of power possible. When powered-down, the PHY does not perform any form of Energy Detection, and does not generate any energy (NLPs) on the wire itself.
PHY Functionality and Features 11.5 Initialization Note: Section 11.5 through Section 11.14 apply only to the 82541xx and 82547GI/EI Ethernet controllers. At power-up or reset, the PHY core performs the initialization as shown in Figure 11-1. The software driver has access to the PHY register 0d, bits 15 and 11 for PHY reset and PHY Power Down control, respectively. Power-up or Reset Read H/W Control Interface Initialize MDIO Registers Pass control to MDIO Interface Figure 11-1.
PHY Functionality and Features 11.6 Determining Link State The PHY and its link partner determine the type of link established through one of three methods: • Auto-Negotiation • Parallel Detection • Forced Operation Auto-Negotiation is the only method allowed by the 802.3ab standard for establishing a 1000BASE-T link, although forced operation could be used for test purposes. For 10/100 links, any of the three methods can be used. The sections that follow discuss each in greater detail.
PHY Functionality and Features 11.6.1 False Link When the PHY is first powered on, reset, or encounters a link down state, it must determine the line speed and operating conditions to use for the network link. The PHY first checks the MDIO registers (initialized via the Hardware Control Interface or written by software) for operating instructions.
PHY Functionality and Features 11.6.3 Auto Negotiation The PHY supports the IEEE 802.3u Auto-Negotiation scheme with next page capability. Next Page exchange uses PHY register 7d to send information and PHY register 8d to receive them. Next Page exchange can only occur if both ends of the link advertise their ability to exchange Next Pages. 11.6.4 Parallel Detection Parallel detection can only be used to establish 10 and 100 links.
PHY Functionality and Features 11.7.3 10BASE-T For 10BASE-T links, the PHY and its link partner begin exchanging Normal Link Pulses (NLPs). The PHY transmits an NLP every 16 ms, and expects to receive one every 10 to 20 ms. The link is maintained as long as normal link pulses are received. 11.8 Link Enhancements The PHY offers two enhanced link functions, each of which are discussed in the sections that follow: • SmartSpeed • Flow Control 11.8.
PHY Functionality and Features Table 10-2 lists the intended operation for the various settings of ASM_DIR and Pause. This information is provided for reference only; it is the responsibility of the MAC to implement the correct function. The PHY merely enables the two MACs to communicate their abilities to each other. Table 10-2.
PHY Functionality and Features 11.10.1 Powerdown via the PHY Register The PHY can be powered down using the control bit found in PHY register 0d, bit 11. This bit powers down a significant portion of the port but clocks to the register section remain active. This enables the PHY management interface to remain active during power-down. The power-down bit is active high.
PHY Functionality and Features MAC Interface 8 8 Trellis Viterbi Encoder/ Decoder Side-stream Scrambler / Descrambler 4 DSP 4 ECHO, NEXT, FEXT Cancellers 4DPAM5 Encoder AGC, A/D, Timing Recovery Pulse Shaper, DAC, Filter Hybrid Line Driver Line Interface Figure 11-3.
PHY Functionality and Features 11.11.2 Transmit Functions This section describes functions used when the Media Access Controller (MAC) transmits data through the PHY and out onto the twisted-pair connection. 11.11.2.1 Scrambler The scrambler randomizes the transmitted data. The purpose of scrambling is two fold: 1. Scrambling eliminates repeating data patterns from the 4DPAM5 waveform to reduce EMI. 2. Each channel (A, B, C, D) gets a unique signature that the receiver uses for identification.
PHY Functionality and Features 11.11.3.4 Spectral Shaper This function causes the 4DPAM5 waveform to have a spectral signature that is very close to that of the MLT3 waveform used by 100BASE-TX. This enables 1000BASE-T to take advantage of infrastructure (cables, magnetics) designed for 100BASE-TX. The shaper works by transmitting 75% of a 4DPAM5 code in the current baud period, and adding the remaining 25% into the next baud period. 11.11.3.
PHY Functionality and Features D0 D1 D2 D3 GMII Polynomial 8 bits Descrambler 8 bits D4 D5 DSP Receiver PAM-5 Encoded Input from 4-Pair UTP Line D6 D7 Figure 11-5. 1000BASE-T Receive Flow 11.11.4 Receive Functions This section describes function blocks that are used when the PHY receives data from the twisted pair interface and passes it back to the MAC. 11.11.4.
PHY Functionality and Features • Far-end crosstalk (FEXT) • Propagation delay variations between channels of up to 120 ns. • Extraneous tones that have been coupled into the receive path. The adaptive filter coefficients are initially set during the training phase. They are continuously adjusted (adaptive equalization) during operation through the decision-feedback loop. 11.11.4.
PHY Functionality and Features 11.13.1 Link Test In 10 Mbps mode, the PHY always transmits link pulses. If the Link Test Function is enabled, it monitors the connection for link pulses. Once it detects 2 to 7 link pulses, data transmission is enabled and remains enabled as long as the link pulses or data reception continues. If the link pulses stop, the data transmission is disabled. If the Link Test function is disabled, the PHY might transmit packets regardless of detected link pulses.
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Dual Port Characteristics 12 Dual Port Characteristics 12.1 Introduction1 The 82546GB/EB architecture includes two instances of both the MAC and PHY (see Figure 2-1). With both MAC/PHY pairs operating, the Ethernet controller appears as a multi-function PCI device containing two identically-functioning devices.
Dual Port Characteristics Byte Offset Byte 0 Byte 1 Byte 2 24h Base Address 5 28h Cardbus CIS Pointer (not used) 2Ch Subsystem ID 30h Subsystem Vendor ID Expansion ROM Base Address 34h Reserved 38h 3Ch Byte 3 Cap_Ptr Reserved Max_Latency 00h Min_Grant FFh Interrupt Pin 01h or 00h) Interrupt Line 00h Many of the fields of the PCI header space contain hardware default values that are either fixed or can be overridden using EEPROM, but cannot be independently specified for each logical LA
Dual Port Characteristics The following fields are implemented unique to each LAN device: Device ID The Device ID reflected for each LAN device can be independently specified via EEPROM. Command, Status Each LAN device implements its own command/status registers. Latency Timer, Cache Line Size Each LAN device implements these registers uniquely. The system should program these fields identically for each LAN to ensure consistent behavior and performance of each device.
Dual Port Characteristics 12.3 Shared EEPROM The Ethernet controller uses a single EEPROM device to configure hardware default parameters for both LAN devices, including Ethernet Individual Addresses (IA), LED behaviors, receive packet-filters for manageability and wakeup capability, etc. Certain EEPROM words are used to specify hardware parameters which are LAN device-independent (such as those that affect circuits behavior). Other EEPROM words are associated with a specific LAN device.
Dual Port Characteristics The result of multiple LAN devices’ reading EEPROM is that power-on and reset-initiated EEPROM read sequences might appear slightly differently from the sequences illustrated during the discussion of power-state transitions (Section 6.3.2). Those illustrations indicate EEPROM read periods without distinguishing between reads by LAN A versus LAN B devices. At initial power-on, both LAN devices always execute an EEPROM read sequence.
Dual Port Characteristics Note: Access contention to FLASH by both LAN devices is more than likely to result in indeterminate data results (during read transactions), corrupted FLASH (during write transactions), or other unpredictable behavior. To avoid this contention, accesses from both LAN devices MUST be synchronized using external software synchronization of the memory or I/O transactions responsible for the access.
Dual Port Characteristics 12.5.3 Multi-Function Advertisement If one of the LAN devices is disabled, the Ethernet controller no longer is a multi-function device. It normally reports a 01h in the PCI Configuration Header field Header Type, indicating multifunction capability. However, if a LAN id disabled, it reports a 0h in this filed to signify singlefunction capability. 12.5.
Dual Port Characteristics 12.5.
Register Descriptions 13 Register Descriptions 13.1 Introduction This section details the state inside the PCI/PCI-X Family of Gigabit Ethernet Controllers that are visible to the programmer. In some cases, it describes hardware structures invisible to software in order to clarify a concept.
Register Descriptions • Reserved and/or undefined addresses. Any register not explicitly declared in this specification should be considered to be reserved and should not be written. Writing to reserved or undefined register addresses can cause indeterminate behavior. Reads from reserved or undefined configuration register addresses can return indeterminate values unless read values are explicitly stated for specific addresses. • Initial values.
Register Descriptions 13.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash1 To support pre-boot operation (prior to the allocation of physical memory base addresses), all internal registers, memories, and Flash can be accessed using I/O operations. I/O accesses are supported only if an I/O Base Address is allocated and mapped (BAR2 or BAR4, see Section 4.1), the BAR contains a valid (non-zero value), and I/O address decoding is enabled in the PCI/PCIX configuration.
Register Descriptions The IODATA register can be written as a byte, word, or Dword access when the IOADDR register contains a value for the Flash (80000h - FFFFFh). In this case, the value in IOADDR must be properly aligned to the data value. Additionally, the lower 2 bits of the IODATA PCI-X access must correspond to the byte, word, or Dword access.Table 13-1 lists the supported configurations: Table 13-1.
Register Descriptions Table 13-2.
Register Descriptions Category Abbreviation Name R/W Page TX DMA 03000h TXDMAC TX DMA Control (applicable to the 82544GC/ EI only) TX DMA 03828h TXDCTL Transmit Descriptor Control R/W 315 TADV Transmit Absolute Interrupt Delay Timer (not applicable to the 82544GC/EI) R/W 317 TX DMA 216 Offset 0282Ch R/W 315 TX DMA 03830h TSPMT TCP Segmentation Pad and Threshold R/W 318 RX DMA 02828h RXDCTL Receive Descriptor Control R/W 320 RX DMA 05000h RXCSUM Receive Checksum Contr
Register Descriptions Category Offset Abbreviation Name R/W Page Statistics 04054h XOFFTXC XOFF Transmitted Count R 345 Statistics 04058h FCRUC FC Received Unsupported Count R/W 346 Statistics 0405Ch PRC64 Packets Received (64 Bytes) Count R/W 346 Statistics 04060h PRC127 Packets Received (65-127 Bytes) Count R/W 347 Statistics 04064h PRC255 Packets Received (128-255 Bytes) Count R/W 347 Statistics 04068h PRC511 Packets Received (256-511 Bytes) Count R/W 348 Statis
Register Descriptions Category Diagnostic Note: Abbreviation TDFT Name R/W Page Transmit Data FIFO Tail R/W 367 Diagnostic 03420h TDFHS Transmit Data FIFO Head Saved Register R/W 367 Diagnostic 03428h TDFTS Transmit Data FIFO Tail Saved Register R/W 368 Diagnostic 03430h TDFPC Transmit Data FIFO Packet Count R/W 368 Diagnostic 10000h1FFFCh PBM Packet Buffer Memory (n) R/W 369 The PHY registers are accessed indirectly through the MDI/O interface described in Section 8.2.
Register Descriptions 13.3 PCI-X Register Access Split1 The PCI-X specification states that accesses to internal device memory spaces must complete within a specific target initial latency, or else the device should signal that it completes the transaction later using a split-completion operation. Due to internal access latencies, read accesses to most device registers in the Ethernet controller exceeds target initial-access latencies, and therefore are split.
Register Descriptions Category Offset Abbreviation Name Interrupt 000D0h IMS Interrupt Mask Set/Read Interrupt 000D8h IMC Interrupt Mask Clear Transmit 00400h TCTL Transmit Control The EEPROM configuration bit “Force CSR Read Split” (Initialization Control Word 2, word 0Fh) provides the ability to configure the device to split all internal register accesses, rather than providing non-split behavior for the registers listed. 13.
Register Descriptions Table 13-3. CTRL Register Bit Description 31 0 Device Control Bits Field FD Reserved Bit(s) 0 2:1 Initial Value 1b 0b1 Description Full-Duplex Enables software to override the hardware Auto-Negotiation function. The FD sets the duplex mode only if CTRL.FRCDPLX is set. When cleared, the Ethernet controller operates in half-duplex; when set, the Ethernet controller operates in full-duplex.
Register Descriptions Field SLU ILOS 6 7 Initial Value Description 0b Set Link Up In TBI mode/internal SerDes, provides manual link configuration. When set, the Link Up signal is forced high once receiver synchronization is achieved (LOS not asserted) using CTRL.FD to determine the duplex mode. This operation bypasses the link configuration process. If Auto-Negotiation is enabled (TXCW.ANE equals 1b), then Set Link Up is ignored.
Register Descriptions Bit(s) Initial Value Description FRCDPLX 12 0b Force Duplex When set, software can override the duplex indication from the PHY which is in internal PHY mode. When set the CTRL.FD bit sets duplex. When cleared, the CTRL.FD is ignored. Reserved 17:13 0b Reserved Should be written with 0b to ensure future compatibility. Read as 0b 0b2 SDP0 Data Value. Used to read (write) value of softwarecontrollable IO pin SDP0.
Register Descriptions Field RST RFCE 26 27 Initial Value Description 0b Device Reset 0b = normal; 1b = reset. Self clearing. When set, it globally resets the entire Ethernet controller with the exception of the PCI configuration registers. All registers (receive, transmit, interrupt, statistics, etc.), and state machines are set to their power-on reset values. This reset is equivalent to a PCI reset, with the one exception being that the PCI configuration registers are not reset.
Register Descriptions The ADVD3WUC bit (Advertise D3Cold Wakeup Capability Enable control) allows the AUX_PWR pin to determine whether D3Cold support is advertised. If full 1 Gb/s operation in D3 state is desired but the system’s power requirements in this mode would exceed the D3Cold Wakeup-Enabled specification limit (375 mA at 3.3 V dc), this bit can be used to prevent the capability from being advertised to the system.
Register Descriptions Table 13-5. Status Register Bit Description 31 13 12 Reserved Field FD LU Function ID TXOFF TBIMODE 226 Initial Value Bit(s) 0 1 3:2 4 5 0 Status Description X Link Full Duplex configuration Indication When cleared, the Ethernet controller operates in half-duplex; when set, the Ethernet controller operates in Full duplex. The FD provides the duplex setting status of the Ethernet controller as set by either Hardware Auto-Negotiation function, or by software.
Register Descriptions Field SPEED Initial Value Bit(s) 7:6 Description X Link speed setting Indicates the configured speed of the link. These bits are either forced by software when forcing the link speed through the CTRL.SPEED control bits, automatically set by hardware when Auto-Speed Detection is enabled or reflect the internal indication inputs from the PHY. When Auto-Speed Detection is enabled, the Ethernet controller’s speed is configured only once after the internal link is asserted.
Register Descriptions 13.4.3 EEPROM/Flash Control & Data Register EECD (00010h; R/W) This register provides a simplified interface for software accesses to the EEPROM. Software controls the EEPROM by successive writes to this register. Data and address information is clocked into the EEPROM by software toggling the EECD.SK bit (2) of this register with EECD.CS set to 1b. Data output from the EEPROM is latched into bit 3 of this register and can be accessed by software through reads of this register.
Register Descriptions Field Bit Initial Value Description EE_REQ 61 0b Request EEPROM Access The software must write a 1b to this bit to get direct EEPROM access. It has access when EE_GNT is 1b. When the software completes the access it must write a 0b. EE_GNT 71 0b Grant EEPROM Access When this bit is 1b the software can access the EEPROM using the SK, CS, DI, and DO bits.
Register Descriptions 13.4.4 EEPROM Read Register1 EERD (00014h; RW) Table 13-7. EEPROM Read Register Bit Description 31 16 Data Field 1. Bit(s) 15 8 Address Initial Value 7 5 RSV. 4 3 DONE 1 RSV. 0 START Description START 0 0b Start Read Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at the address stored in the EE_ADDR field and then storing the result in the EE_DATA field. This bit is self-clearing. Reserved 3:1 0b Reserved. Reads as 0b.
Register Descriptions Table 13-8. EEPROM Read Register Bit Description (82541xx and 82547GI/EI) 31 16 Data Field START Bit(s) 0 Initial Value 15 2 Address 1 0 DONE START Description 0b Start Read Writing a 1b to this bit causes the EEPROM to read a (16-bit) word at the address stored in the EE_ADDR field and then storing the result in the EE_DATA field. This bit is self-clearing. DONE 1 0b Read Done Set to 1b when the EEPROM read completes. Set to 0b when the EEPROM read is in progress.
Register Descriptions 13.4.5 Flash Access1 FLA (0001Ch; R/W) This register provides software direct access to the Flash memory. Software can control the Flash device by successive writes to this register. Data and address information is clocked into the Flash memory by software toggling the FL_SCK bit (0) of this register with FL_CE set to 1b. Data output from the Flash memory is latched into bit three of this register via the internal 125 MHz clock and is accessed by software via reads of this register.
Register Descriptions 13.4.6 Extended Device Control Register CTRL_EXT (00018h, R/W) This register and the Device Control register (CTRL) controls the major operational modes for the Ethernet controller. CTRL_EXT provides extended control of the Ethernet controller functionality over the Device Control register (CTRL). Note: See Table 13-12 and Table 13-13 for the 82544GC/EI. Table 13-10.
Register Descriptions Field Bit(s) Initial Value SDP6_IODIR SDP2_IODIR (82541xx and 82547GI/EI) 10 0b1 SDP6[2] Pin Directionality. Controls whether software-controllable pin SDP6[2] is configured as an input or output (0b = input, 1b = output). Initial value is EEPROM-configurable. This bit is not affected by software or system reset, only by initial power-on or direct software writes. 0b1 SDP7[2] Pin Directionality.
Register Descriptions Field VREG POWER DOWN Initial Value Bit(s) 21 Description 0b Voltage Regulator Power Down (82541xx and 82547GI/EI only) 0b = Normal operation. 1b = Voltage regulators power down. This bit is initialized from the EEPROM. Note: This is a reserved bit for all remaining Ethernet controllers. Set to 0b. LINK_MODE 23:22 0b Link Mode. This controls which interface is used to talk to the link.
Register Descriptions Table 13-12. 82544GC/EI CTRL_EXT Register Bit Description 31 16 15 Reserved Field GPI_EN SWDPINSHI SWDPIOHI ASDCHK EE_RST IPS 236 Initial Value Bit(s) 3:0 7:6, 4 11:10, 8 12 13 14 0 Extended Device Control Bits Description 0 General Purpose Interrupt Enables These bits determine whether the upper three software definable pins SDP[7:6] and SDP[4] are mapped to the ICR.GPI interrupt bits.
Register Descriptions Field Initial Value Bit(s) Description SPD_BYPS 15 0 Speed Select Bypass When set to 1b, all speed detection mechanisms are bypassed, and the Ethernet controller is immediately set to the speed indicated by CTRL.SPEED. This might be used to override the hardware clock switching circuitry and give full control to software. SPD_BYPS differs from the CTRL.
Register Descriptions 13.4.7 MDI Control Register MDIC (00020h; R/W) Software uses this register to read or write Management Data Interface (MDI) registers in the internal PHY.
Register Descriptions Table 13-14. MDI Control Register Bit Description 31 30 29 28 RSV E I R Field 27 26 25 21 20 16 15 OP PHY Initial Value Bit(s) 0 REG DATA Description DATA 15:0 X Data In a Write command, software places the data bits and the Ethernet controller shifts them out to the PHY. In a Read command, the Ethernet controller reads these bits serially from the PHY and software can read them from this location. REGADD 20:16 0b PHY Register Address: Reg. 0, 1, 2, ...
Register Descriptions 13.4.7.1 PHY Registers This document uses a special nomenclature to define the read/write mode of individual bits in each register. See Table 13-15. For all binary equations appearing in the register map, the symbol “|” is equivalent to a binary OR operation. Table 13-15. PHY Register Bit Mode Definitions Register Mode 240 Description LH Latched High. Event is latched and erased when read. LL Latched Low. Event is latched and erased when read.
Register Descriptions 13.4.7.1.1 PHY Control Register PCTRL (00d; R/W) Table 13-16. PHY Control Register Bit Description Field Reserved Speed Selection (MSB) Collision Test Duplex Mode Bit(s) Description HW Rst SW Rst 5:0 These bits are reserved and should be set to 000000b. RO RW1 Always 000000b 6 Speed Selection is determined by bits 6 (MSB) and 13 (LSB) as follows.
Register Descriptions Table 13-16. PHY Control Register Bit Description Field Power Down 242 Bit(s) 11 Description Mode 1b = Power down. 0b = Normal operation. Power down shuts down the Ethernet controller except for the MAC interface if the MAC interface power down bit is set to 1b. If it equals 0b, then the MAC interface also shuts down. For the 82544GC/EI, power down has no effect on the 125CLK output if the Disable 125CLK bit is set to 0b.
Register Descriptions Table 13-16. PHY Control Register Bit Description Field Auto-Negotiation Enable Bit(s) 12 Description 1b = Enable Auto-Negotiation Process. 0b = Disable Auto-Negotiation Process. A write to this bit does not take effect until a software reset is asserted, Restart Auto-Negotiation is asserted, or Power Down transitions from power down to normal operation.
Register Descriptions 13.4.7.1.2 PHY Status Register PSTATUS (01d; R) Table 13-17. PHY Status Register Bit Description Field Description Mode HW Rst SW Rst Extended Capability 0 1b = Extended register capabilities. RO Always 1b Jabber Detect 1 1b = Jabber condition detected. 0b = Jabber condition not detected. RO,L H 0b 0b Link Status 2 1b = Link is up. 0b = Link is down. This register indicates whether link was lost after the last read.
Register Descriptions Table 13-17. PHY Status Register Bit Description Field 10 Mb/s Full Duplex 100BASE-X Half Duplex 100BASE-X Full Duplex 100BASE-T4 Software Developer’s Manual Bit(s) 12 13 14 15 Description 1b = PHY able to perform full duplex 10BASE-T. 0b = PHY not able to perform full duplex 10BASE-T. 82544GC/EI only: Bit 14 = Bit 13 = Bit 12 = Bit 11 = (MODE[3:0] is not any of xx01b, 1x00b, 001xb, 0111b). 1b = PHY able to perform half duplex 100BASE-X.
Register Descriptions 13.4.7.1.3 PHY Identifier Register (LSB) PID (02d; R) Table 13-18. PHY Identifier Bit Description Field Bit(s) Organizationally Unique Identifier Bit 18:31 1. 2. 13.4.7.1.4 Description Mode 0000_0001_0100_0001b OUI is 005043h. 15:0 HW Rst SW Rst Always 0141h The PHY identifier composed of bits 3 through 18 of the OUI (Organizationally Unique Identifier)2 RO Always 02A8h2 PHY ID number for the 82541xx and 82547GI/EI only. 82541xx and 82547GI/EI only.
Register Descriptions 13.4.7.1.5 Auto-Negotiation Advertisement Register ANA (04d; R/W) Table 13-20. Auto-Negotiation Advertisement Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 00001b = 802.3 For the 82541xx and 82547GI/EI: Other combinations are reserved. Selector Field 4:0 Unspecified or reserved combinations should not be transmitted. RO Always 00001b Note: Setting this field to a value other than 00001b can cause auto negotiation to fail. 1b = Advertise.
Register Descriptions Table 13-20. Auto-Negotiation Advertisement Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 1b = Advertise. 1b 0b = Not advertised. Values programmed in the AutoNegotiation advertisement register have no effect unless AutoNegotiation is restarted (PHY Control Register) or link goes down. 100BASE-TX Half Duplex 100Base-TX (82541xx and 82547GI/EI) 7 This bit can be overridden by the PHY Control Register.
Register Descriptions Table 13-20. Auto-Negotiation Advertisement Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 1b = Asymmetric Pause. 0b = No asymmetric Pause. Asymmetric Pause ASM_DIR for the (82541xx and 82547GI/EI) 11 Values programmed in the AutoNegotiation advertisement register have no effect unless AutoNegotiation is restarted (PHY Control Register) or link goes down. 0b R/W 82541xx and 82547GI/EI only: Advertise Asymmetric Pause direction bit.
Register Descriptions 82544GC/EI Only: Table 13-21. Auto-Negotiation Advertisement Register Bit Description (MODE[3:0] is one of 001xb, 0111b) Field Description Mode HW Rst SW Rst 4:0 Values programmed in this register have no effect unless Auto-Negotiation is restarted (PHY Control Register) or the link goes down. Reserved bit is R/W to allow forward compatibility with future IEEE standards.
Register Descriptions Table 13-21. Auto-Negotiation Advertisement Register Bit Description (MODE[3:0] is one of 001xb, 0111b) Field Bit(s) Next Page 13.4.7.1.6 15 Description 0b = Not advertised Values programmed in this register have no effect unless Auto-Negotiation is restarted (PHY Control Register) or the link goes down. Next Page is not supported in 1000BASE-X mode. Mode RO HW Rst SW Rst Always 0b Link Partner Ability Register (Base Page) LPA (05d; R) Table 13-22.
Register Descriptions 82544GC/EI Only: Table 13-23. Link Partner Ability Register (Base Page) Bit Description1 Field Description Mode HW Rst SW Rst Reserved 4:0 Reserved. Should be set to 00000b. RO 00000b 00000b 10BASE-TX Half Duplex 5 1b = 10 Base-TX half duplex is available. 0b = 10 Base-TX half duplex is not available. RO 0b 0b 10BASE-TX Full Duplex 6 1b = 10 Base-TX full duplex is available. 0b = 10 Base-TX full duplex is not available.
Register Descriptions 82541xx and 82547GI/EI Only: Table 13-24. PHY Link Page Ability Bit Description1 Field Bit(s) Description Mode HW Rst SW Rst Selector Field [4:0] 4:0 <00001> = IEEE 802.3 Other combinations are reserved. Unspecified or reserved combinations shall not be transmitted. If field does not match PHY Register 4, bits 4:0, the AN process does not complete and no HCD is selected. 10BASE-T 5 1b = Link Partner is 10BASE-T capable. 0b = Link Partner is not 10BASE-T capable.
Register Descriptions 13.4.7.1.7 Auto-Negotiation Expansion Register ANE (06d; R) Table 13-25. Auto-Negotiation Expansion Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 0 1b = Link Partner is Auto-Negotiation able. 0b = Link Partner is not AutoNegotiation able. RO 0b 0b Page Received 1 1b = A New Page has been received. 0b = A New Page has not been received.
Register Descriptions 13.4.7.1.8 Next Page Transmit Register NPT (07d; R/W) Table 13-26. Next Page Transmit Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 10:0 Transmit Code Word Bit 10:0. 82541xx and 82547GI/EI only: 11-bit message code field. R/W 001h 001h 11 Transmit Code Word Bit 11. 82541xx and 82547GI/EI only: 1b = Previous value of the transmitted Link Code Word = logical 0. 0b = Previous value of the transmitted Link Code Word = logical 1.
Register Descriptions 13.4.7.1.9 Link Partner Next Page Register LPN (08d; R) Table 13-27. Link Partner Next Page Register Bit Description Bit(s) 10:0 11 12 13 14 15 256 Field Description Mode HW Rst SW Rst Message/ Unformatted Field Received Code Word Bit 10:0. 82541xx and 82547GI/EI only: 11-bit message code field. RO 000h 000h Toggle Received Code Word Bit 11. 82541xx and 82547GI/EI only: 1b = Previous value of the transmitted Link Code Word = a logic 0.
Register Descriptions 13.4.7.1.10 1000BASE-T Control Register GCON (09d; R/W) Table 13-28. 1000BASE-T Control Register Bit Description Bit(s) 7:0 8 9 10 11 Field Description Reserved Reserved. Should be set to 00000000b. 1000BASE-T Half Duplex 1b = Advertise. 0b = Not advertised. 82544GC/EI only: Bit 8 = ANEG[2]. 82541xx and 82547GI/EI only: 1b = DTE is 1000BASE-T capable. 0b = DTE is not 1000BASE-T capable. This bit is used by Smart Negotiation. 1000BASE-T Full Duplex 1b = Advertise.
Register Descriptions Table 13-28. 1000BASE-T Control Register Bit Description Bit(s) Field Description Mode HW Rst SW Rst 000b = Normal Mode. 001b = Test Mode 1 - Transmit Waveform Test. 15:13 010b = Test Mode 2 - Transmit Jitter Test (MASTER mode). Test mode R/W 011b = Test Mode 3 - Transmit Jitter Test (SLAVE mode). 000b 000b 100b = Test Mode 4 - Transmit Distortion Test. 101b, 110b, 111b = Reserved. 1. 2. 3.
Register Descriptions Table 14-29. 1000BASE-T Status Register Bit Description Field Bit(s) Local Receiver Status MASTER/SLAVE Configuration Resolution MASTER/SLAVE Configuration Fault 13.4.7.1.12 Description Mode HW Rst SW Rst 13 1b = Local Receiver OK. 0b = Local Receiver Not OK. RO 0b 0b 14 1b = Local PHY configuration resolved to MASTER. 0b = Local PHY configuration resolved to SLAVE. RO 0b 0b 15 1b = MASTER/SLAVE configuration fault detected.
Register Descriptions 13.4.7.1.13 PHY Specific Control Register PSCON (16d; R/W) Table 13-31. PHY Specific Control Register Bit Description Description Field Bit(s) Mode 1000BASE-T HW Rst SW Rst 10/100BASE-T 1b = Disable jabber function. Disable Jabber 0 0b = Enable jabber function. Jabber has effect only in 10BASE-T half duplex mode. R/W 0b Retain R/W 0b Retain R/W 0b Retain R/W 1b Update R/W DIS_ 125CLK1 Update 1b = Polarity Reversal Disabled.
Register Descriptions Table 13-31. PHY Specific Control Register Bit Description Description Field Bit(s) Mode 1000BASE-T HW Rst SW Rst 10/100BASE-T Energy Detect. 0xb = Off. Energy Detect 9:8 10b = Sense only on receive. R/W 0b Retain R/W 0b Retain R/W 0b Retain R/W 00b Retain R/W 00b Retain 11b = Sense and periodically transmit NLP. 1b = Force link good. 0 b = Normal operation.
Register Descriptions Table 13-32. PHY Port Configuration Register Bit Description Field Auto MDIX Parallel Detect Bypass Bit(s) 4 Description Mode Auto_MDIX Parallel Detect Bypass. Bypasses the fix to IEEE auto-MDIX algorithm for the case where the PHY is in forced-speed mode and the link partner is auto-negotiating. 1b = Strict 802.3 Auto-MDIX algorithm. 0b = Auto-MDIX algorithm handles Auto-Negotiation disabled modes.
Register Descriptions 13.4.7.1.14 PHY Specific Status Register PSSTAT (17d; R) Table 13-33. PHY Specific Status Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst Jabber (real time) 0 1b = Jabber. 0 = No jabber. RO 0b Retain Polarity (real time) 1 1b = Reversed. 0b = Normal. RO 0b 0b 2 1b = Receive pause enabled. 0b = Receive pause disabled. The Receive Pause Enable bit is valid only after the Speed and Duplex Resolved bit (11) is set.
Register Descriptions Table 13-33. PHY Specific Status Register Bit Description Field Description Mode HW Rst SW Rst Speed and Duplex Resolved 11 1b = Resolved. 0b = Not resolved. Speed, Duplex, MDI Crossover Status, Transmit Pause Enable, and Receive Pause Enable bits are valid only after the Speed and Duplex Resolved bit (11) is set. This occurs when AutoNegotiation is completed or AutoNegotiation is disabled. Page Received 12 1b = Page received. 0b = Page not received.
Register Descriptions PHY Port Status 1 Register (82541xx and 82547GI/EI Only) PPSTAT (17d; R) Table 13-34. PHY Status 1 Register Bit Description Field LFIT Indicator Bit(s) 0 Description Status bit indicating the AutoNegotiation Link Fail Inhibit Timer has expired. This indicates that the AutoNegotiation process completed page exchanges but was unable to bring up the selected MAU’s link. 1b = Auto-Negotiation has aborted Link establishment following normal page exchange.
Register Descriptions Table 13-34. PHY Status 1 Register Bit Description Field Bit(s) Transmit Status 13 Description Mode 1b = PHY currently transmitting a packet. 0b = PHY transmitter is IDLE. HW Rst SW Rst RO 0b 0b RO 0b 0b When in loopback, this bit reads as 0b. 00b = Reserved. 01b = PHY operating in 10BASE-T mode. Data Rate 15:14 10b = PHY operating in 100BASE-TX mode. 11b = PHY operating in 1000BASE-T mode. 13.4.7.1.15 PHY Interrupt Enable Register PINTE (18d; R/W) Table 13-35.
Register Descriptions Table 13-35. PHY Interrupt Enable Bit Description Field Bit(s) Description Mode HW Rst SW Rst Page Received Interrupt Enable 12 1b = Interrupt enable. 0b = Interrupt disable. R/W 0b Retain Duplex Changed Interrupt Enable 13 1b = Interrupt enable. 0b = Interrupt disable. R/W 0b Retain Speed Changed Interrupt Enable 14 1b = Interrupt enable. 0b = Interrupt disable. R/W 0b Retain Auto-Negotiation Error Interrupt Enable 15 1b = Interrupt enable.
Register Descriptions Table 13-36. PHY Port Control Register Bit Description Field Bit(s) MDI-X Mode 13 Description Mode Force MDI-X mode. Valid only when operating in manual mode. (PHY register 18, bit 12 = 0b. HW Rst SW Rst R/W 0b 0b R/W 0b 0b R/W 0b 0b 1b = MDI-X (cross over). 0b = MDI (no cross over). Reserved 14 Always read as 0b. Write to 0b for normal operation.
Register Descriptions Table 13-37. PHY Interrupt Status Bit Description Field Bit(s) Description Mode HW Rst SW Rst FIFO Over/Underflow 7 1b = Over/Underflow Error. 0b = No FIFO Error. RO, LH 0b 0b False Carrier 8 1b = False carrier. 0b = No false carrier. RO, LH 0b 0b Symbol Error 9 1b = Symbol error. 0b = No symbol error. RO, LH 0b 0b Link Status Changed 10 1b = Link status changed. 0b = Link status not changed.
Register Descriptions Table 13-38. PHY Link Health Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst Auto-Negotiation Fault 6 Auto-Negotiate Fault: This is the logical OR of PHY register 1, bit 4, PHY register 6, bit 4, and PHY register 10, bit 15. RO 0b 0b Reserved 7 Always read as 0b. RO 0b 0b LH 0b 0b RO/ LH 0b 0b Mode: Data Err[0] 8 10: 10 Mbps polarity error. 100: Symbol error. 1000: Gig idle error. Mode: Data Err[1] 9 10: Reserved.
Register Descriptions 13.4.7.1.17 Extended PHY Specific Control Register 11 EPSCON1 (20d; R/W) Table 13-39. Extended PHY Specific Control 1 Bit Description1 Field Description Mode HW Rst SW Rst Reserved 1:0 00b R/W 00b Retain Reserved 3 0b R/W 0b 0 6:4 Reserved. Should be set to 0b. Changes to this bit are disruptive to the normal operation; any change to this register must be followed by software reset to take effect. R/W 110b Update 7 Reserved. Should be set to 0b.
Register Descriptions GMII FIFO Register (82541xx and 82547GI/EI Only) PFIFO (20d; R/W) Table 13-40. GMII FIFO Register Bit Description Field Bit(s) Description Mode HW Rst SW Rst 3:0 An unsigned integer that stipulates the number of write clocks to delay the read controller after internal GMII’s tx_en is first asserted. This “buffer” protects from underflow at the expense of latency. The maximum value that can be set is 13d or Dh.
Register Descriptions 13.4.7.1.18 PHY Receive Error Counter PREC (21d; R) Table 13-41. PHY Receive Error Counter Bit Description Field Bit(s) Receive Error Count 15:0 Description Error Count. Mode RO,SC HW Rst 0000h SW RST 0000h NOTE: The counter stops at FFFFh and does not roll over. PHY Channel Quality Register (82541xx and 82547GI/EI Only) PCHAN (21d; R) Table 13-42.
Register Descriptions Table 13-43. SPEED_TEN_LED and LINK_ACT_LED Bit Description LED Stretch Disable 5 Disable the SPEED_TEN_LED Extension Logic. 0b = Enable logic. 1b = Disable logic. Note: Only when both the stretch and blink are disabled the input bypasses the blink logic and is muxed out with no sampling (only combinational logic). LED Source Select 9:6 Mux the designated input to LED_ACT_LED. R/W 0001b 0001b LED Blink Disable 10 Disable the LINK_ACT_LED Blink Logic. 0b = Enable logic.
Register Descriptions 13.4.7.1.20 PHY Global Status (82544GC/EI Only) PGSTAT (23d; R) Table 13-44. PHY Global Status Bit Description Field Bit(s) Description Mode HW Rst SW Rst Port 0 Interrupt 0 0b = No Interrupt on Port. 1b = Interrupt on Port. RO 0b 0b Port 1 Interrupt 1 0b = No Interrupt on Port. 1b = Interrupt on Port. RO 0b 0b Port 2 Interrupt 2 0b = No Interrupt on Port. 1b = Interrupt on Port. RO 0b 0b Port 3 Interrupt 3 0b = No Interrupt on Port. 1b = Interrupt on Port.
Register Descriptions Table 13-45. SPEED_100_LED and SPEED_1000_LED Bit Description 13.4.7.1.22 LED Stretch Disable 11 Disable the SPEED_1000_LED Extension Logic. 0b = Enable logic. 1b = Disable logic. Note: Only when both the stretch and blink are disabled the input bypasses the blink logic and is muxed out with no sampling (only combinational logic). Reserved 15:12 Always read as 0b.
Register Descriptions 13.4.7.1.23 Extended PHY Specific Control Register 2 EPSCON2 (26d; R/W) Table 13-47. Extended PHY Specific Control Register 2 Bit Description Field Bit(s) Description Mode HW Rst SW Rst Fiber Output Amplitude 2:0 111b = 1.2, 100b = 0.9, 001b = 0.6 110b = 1.1, 011b = 0.8, 000b = 0.5 101b = 1.0, 010b = 0.7 R/W 100b Retain Reserved 3 Reserved. Should be set to 1b. R/W 1b 1b Reserved 4 Reserved. Should be set to 0b.
Register Descriptions 13.4.7.1.26 MDI Register 30 Access Window1 R30AW (30d; R/W) Table 13-50. MDI Register 30 Page Select Bit Description Field Bit(s) Register 30 Access 13.4.7.1.27 15:0 Description Mode Provides read/write capability for register selected via MDI register 29. R/W HW Rst 0000h SW Rst 0000h Documented MDI Register 30 Operations1 Unless otherwise specified, no reset operations are required in order for the following operations to take effect. Table 13-51.
Register Descriptions 13.4.7.1.28 PHY Page Select Register (82541xx and 82547GI/EI Only) PPAGE (31d; R/W) Table 13-52. PHY Page Select Register Bit Description Field Bit(s) PAGE_SEL 13.4.8 Description Mode This register is used to swap out the Base Page containing the IEEE registers for Intel reserved test and debug pages residing within the Extended Address space. 15:0 WO HW Rst 0b SW Rst 0b Flow Control Address Low FCAL (00028h; R/W) Flow control packets are defined by IEEE 802.
Register Descriptions Table 13-54. FCAH Register Bit Description 31 16 15 0 Reserved Field 13.4.10 FCAH Initial Value Bit(s) Description FCAH 15:0 X Flow Control Address High Should be programmed with 0100h. Reserved 31:16 0b Reserved Should be written with 0b to ensure future compatibility. Reads as 0b.
Register Descriptions Table 13-56. VET Register Bit Description 31 16 15 0 Reserved Field 13.4.12 VET Initial Value Bit(s) Description VET 15:0 X VLAN EtherType Should be programmed with 8100h. Reserved 31:16 0b Reserved Reads as 0b. Flow Control Transmit Timer Value FCTTV (00170h; R/W) Provides the Pause slot time value to be included in the transmitted XOFF Pause packets. The slot time value that is used is a fixed slot of 64-byte time. Table 13-57.
Register Descriptions 13.4.13 Transmit Configuration Word Register1 TXCW (00178h; R/W) This register is applicable to the TBI mode/internal SerDes mode of operation. For internal PHY operation, program the register to 0000h. For example, clear this register in MMI mode. This register has two meanings, depending on the state of Auto-Negotiation: one as the “AN advertise register” defined by IEEE 802.3z, and the other as a register for software control of the Auto-Negotiation process.
Register Descriptions Field TxConfig ANE Note: 13.4.14 Bit(s) 30 31 Initial Value Description 0b Transmit Config Control bit 0b = Transmit data/idle 1b = Transmit /C/ ordered sets Setting the TxConfig bit causes transmission of /C/ ordered set in a software controlled Auto-Negotiation process (TXCW.ANE=0b). 0b Auto-Negotiation Enable. 1b = Enable the hardware Auto-Negotiation state machine. 0b = Disable the hardware Auto-Negotiation state machine. This bit has the same function as bit 0.
Register Descriptions Table 13-59. RXCW Register Bit Description Field Description RxConfigWord 15:0 X Data received during Auto-Negotiation process. When performing hardware Auto-Negotiation (TXCW.ANE = 1b), the “AN link partner ability base page register” is recorded in the RxConfigWord. When TXCW.ANE is clear, then this register is used by software to perform software based Auto-Negotiation. In that capacity, RxConfigWord records the raw values returned from the Auto-Negotiation process.
Register Descriptions Field RxConfig RxSynchronize ANC 13.4.15 Bit(s) 29 30 31 Initial Value Description 0b /C/ order set reception indication 0b = Receive idle/data stream. 1b = Receiving /C/ order sets. Provides an indication as to whether the interface is receiving /C/ order set, or normal idle/data stream. 82544GC/EI only: Valid only in software Auto-Negotiation mode (TXCW.ANE = 0b). 0b Lost bit synchronization indication 0b = Lost synchronization. 1b = Bit synchronization (bit is LL).
Register Descriptions Table 13-60. LED Control Bit Description1 Field Initial Value Description LED0_MODE 3:0 0010b1 LED0/LINK# Mode. This field specifies the control source for the LED0 output. An initial value of 0010b selects LINK_UP# indication. Reserved 5:4 00b Reserved. Read-only as 0b. Write as 0b for future compatibility. LED0_IVRT 6 0b1 LED0/LINK# Invert. This field specifies the polarity/ inversion of the LED source prior to output or blink control. 0b = do not invert LED source.
Register Descriptions Table 13-61. Mode Encodings for LED Outputs1 Mode 1. Pneumonic State / Event Indicated 0000b LINK_10/1000 Asserted when either 10 or 1000 Mbps link is established and maintained. 0001b LINK_100/1000 Asserted when either 100 or 1000 Mbps link is established and maintained. 0010b LINK_UP Asserted when any speed link is established and maintained. 0011b ACTIVITY Asserted when link is established and packets are being transmitted or receive activity that passes filtering.
Register Descriptions Mode Pneumonic 1111b 13.4.16 GND/LED_OFF State / Event Indicated Always low. Assuming no optional inversion selected, causes output pin low / LED OFF for typical LED circuit. Packet Buffer Allocation PBA (01000H; R/W) This register sets the on-chip receive and transmit storage allocation ratio. The receive allocation value is read/write for the lower seven bits. The receive allocation value must be a multiple of eight (multiple of two for the 82547GI/EI B1 stepping).
Register Descriptions 13.4.17 Interrupt Cause Read Register ICR (000C0H; R) This register contains all interrupt conditions for the Ethernet controller. Each time an interrupt causing event occurs, the corresponding interrupt bit is set in this register. A PCI interrupt is generated each time one of the bits in this register is set, and the corresponding interrupt is enabled through the Interrupt Mask Set/Read IMS Register (see Section 13.4.20). All register bits are cleared upon read.
Register Descriptions Field Bit(s) Initial Value RXT0 7 0b Receiver Timer Interrupt Set when the receiver timer expires. The receiver timer is used for receiver descriptor packing. Timer expiration flushes any accumulated descriptors and sets an interrupt event when enabled. Reserved 8 0b Reserved Reads as 0b. MDAC 9 0b MDI/O Access Complete This bit is set when the MDI/O access is completed. RXCFG 10 0b Receiving /C/ ordered sets Mapped to RXCW.RxConfig.
Register Descriptions Field Reserved 1. 2. Note: 13.4.18 Initial Value Bit(s) 31:17 0b Description Reserved Reads as 0b. The 82540EP/EM, 82541xx, or 82547GI/EI do not support SerDes functionality. Not applicable to the 82544GC/EI. The 82547GI/EI signals interrupts over the CSA port, not a dedicated interrupt pin. Interrupt Throttling Register1 ITR (000C4h; R/W) Field 31 - 16 15 - 0 Reserved INTERVAL Initial Value Bit(s) Description INTERVAL 15:0 0b Minimum inter-interrupt interval.
Register Descriptions 13.4.19 Interrupt Cause Set Register ICS (000C8h; W) Software uses this register to set an interrupt condition. Any bit written with a 1b sets the corresponding interrupt. This results in the corresponding bit being set in the Interrupt Cause Read Register (see Section 13.4.17). A PCI interrupt is generated if one of the bits in this register is set and the corresponding interrupt is enabled through the Interrupt Mask Set/Read Register (see Section 13.4.20).
Register Descriptions Field 13.4.20 Initial Value Bit(s) Description GPI 14:11 X Sets General Purpose Interrupts (82544GC/EI only). GPI 14:13 X Sets General Purpose Interrupts. TXD_LOW 15 X Transmit Descriptor Low Threshold Hit. Not applicable to the 82544GC/EI. SRPD 16 X Small Receive Packet Detected and Transferred. Not applicable to the 82544GC/EI. Reserved 31:17 X Reserved Should be written with 0b to ensure future compatibility.
Register Descriptions Field 13.4.21 Initial Value Bit(s) Description RXSEQ 3 X Sets mask for Receive Sequence Error. This is a reserved bit for the 82541xx and 82547GI/EI. Set to 0b. RXDMT0 4 X Sets mask for Receive Descriptor Minimum Threshold hit. Reserved 5 X Reserved Should be written with 0b to ensure future compatibility. RXO 6 X Sets mask for on Receiver FIFO Overrun. RXT0 7 X Sets mask for Receiver Timer Interrupt.
Register Descriptions Software should write a 1b to the reserved bits to ensure future compatibility. Since this register masks interrupts when 1b is written to the corresponding (defined) bits, then writing 1b to the reserved bits ensures that the software is never called to handle an interrupt that the software is not aware exists. Note: For the 82547GI/EI, programmers need to first write (clear) the IMS and IMC registers due to a Hub Link bus being occupied.
Register Descriptions Field 13.4.22 Initial Value Bit(s) Description TXD_LOW 15 X Clears the mask for Transmit Descriptor Low Threshold hit (not applicable to the 82544GC/EI). SRPD 16 X Clears mask for Small Receive Packet Detect Interrupt (not applicable to the 82544GC/EI). Reserved 31:17 X Reserved Should be written with 1b to ensure future compatibility. Receive Control Register RCTL (00100h; R/W) This register controls all Ethernet controller receiver functions. Table 13-67.
Register Descriptions Field MPE LPE LBM Bit(s) 4 5 7:6 Initial Value Description 0b Multicast Promiscuous Enabled 0b = Disabled. 1b = Enabled. When set, passes without filtering out all received multicast packets. Otherwise, the Ethernet controller accepts or rejects a multicast packet based on its 4096-bit vector multicast filtering table. 0b Long Packet Reception Enable 0b = Disabled. 1b = Enabled. LPE controls whether long packet reception is permitted.
Register Descriptions Field BAM BSIZE VFE 15 17:16 18 Initial Value Description 0b Broadcast Accept Mode. 0 = ignore broadcast; 1 = accept broadcast packets. When set, passes and does not filter out all received broadcast packets. Otherwise, the Ethernet controller accepts, or rejects a broadcast packet only if it matches through perfect or imperfect filters.
Register Descriptions Field Initial Value Bit(s) Description PMCF 23 0b Pass MAC Control Frames 0b = Do not (specially) pass MAC control frames. 1b = Pass any MAC control frame (type field value of 8808h) that does not contain the pause opcode of 0001h. PMCF controls the DMA function of MAC control frames (other than flow control).
Register Descriptions 13.4.23 Flow Control Receive Threshold Low FCRTL (02160h; R/W) This register contains the receive threshold used to determine when to send an XON packet. It counts in units of bytes. Each time the receive FIFO crosses the receive high threshold FCRTH.RTH (filling up), and then crosses the receive low threshold FCRTL.RTL, with FCRTL.XONE enabled, hardware transmits an XON frame. Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process.
Register Descriptions 13.4.24 Flow Control Receive Threshold High FCRTH (02168h; R/W) This register contains the receive threshold used to determine when to send an XOFF packet. It counts in units of bytes. Each time the receive FIFO reaches the fullness indicated by FCRTH, hardware transmits a PAUSE frame if the transmission of flow control frames is enabled (CTRL.TFCE). Flow control reception/transmission are negotiated capabilities by the Auto-Negotiation process.
Register Descriptions 13.4.25 Receive Descriptor Base Address Low RDBAL (02800h;R/W) This register contains the lower bits of the 64-bit descriptor base address. The four low-order register bits are always ignored. The Receive Descriptor Base Address must point to a 16-byte aligned block of data. Table 13-70. RDBAL Register Bit Description 31 4 RDBAL Field 13.4.26 0 0 Initial Value Bit(s) 3 Description 0 3:0 0b Ignored on writes. Returns 0b on reads.
Register Descriptions 13.4.27 Receive Descriptor Length RDLEN (02808h; R/W) This register determines the number of bytes allocated to the circular receive descriptor buffer. This value must be 128-byte aligned (the maximum cache line size). Since each descriptor is 16 bytes in length, the total number of receive descriptors is always a multiple of eight. Table 13-72. RDLEN Register Bit Description 31 20 19 7 6 Reserved Field 13.4.
Register Descriptions 13.4.29 Receive Descriptor Tail RDT (02818h;R/W) This register contains the tail pointers for the receive descriptor buffer. The register points to a 16byte datum. Software writes the tail register to add receive descriptors to the hardware free list for the ring. Table 13-74. RDT Register Bit Description 31 16 15 Reserved Field 13.4.30 Bit(s) 0 RDT Initial Value Description RDT 15:0 0b Receive Descriptor Tail. Reserved 31:16 0b Reserved Reads as 0b.
Register Descriptions This feature operates by initiating a countdown timer upon successfully receiving each packet to system memory. If a subsequent packet is received BEFORE the timer expires, the timer is reinitialized to the programmed value and re-starts its countdown. If the timer expires due to NOT having received a subsequent packet within the programmed interval, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated.
Register Descriptions When this timer is enabled, a separate absolute countdown timer is initiated upon successfully receiving each packet to system memory. When this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated. Setting this register to 0b disables the absolute timer mechanism (the RDTR register should be used with a value of 0b to cause immediate interrupts for all receive packets).
Register Descriptions Table 13-76. TCTL Register Bit Description 31 26 25 Reserved 22 21 12 11 CNTL Bits Field Reserved Bit(s) 0 4 3 COLD Initial Value CT 0 CNTL Bits Description 0b Reserved Write as 0b for future compatibility. EN 1 0b Transmit Enable The transmitter is enabled when this bit is set to 1b. Writing 0b to this bit stops transmission after any in progress packets are sent. Data remains in the transmit FIFO until the device is re-enabled.
Register Descriptions Field Initial Value Bit(s) Reserved 23 RTLC 24 Description 0b Reserved Read as 0b. Should be written with 0b for future compatibility. 0b Re-transmit on Late Collision When set, enables the Ethernet controller to re-transmit on a late collision event. The collision window is speed dependent. For example, 64 bytes for 10/100 Mb/s and 512 bytes for 1000Mb/s operation.
Register Descriptions Table 13-77. TIPG Register Bit Description 31 30 29 20 Reserved IPGR2 Field 10 9 IPGR1 Initial Value Bit(s) 19 0 IPGT Description IPG Transmit Time Specifies the IPG time for back-to-back packet transmissions Measured in increments of the MAC clock: • 8 ns MAC clock when operating @ 1 Gbps. • 80 ns MAC clock when operating @ 100 Mbps. IPGT IPGR1 9:0 19:10 X X • 800 ns MAC clock when operating @ 10 Mbps.
Register Descriptions Field Initial Value Bit(s) Description IPG Receive Time 2 Specifies the total length of the IPG time for non back-to-back transmissions. Measured in increments of the MAC clock: • 8 ns MAC clock when operating @ 1 Gbps (82544GC/EI only). • 80 ns MAC clock when operating @ 100 Mbps 13.4.35 IPGR2 29:20 X Reserved 31:30 X • 800 ns MAC clock when operating @ 10 Mbps.
Register Descriptions Table 13-78. AIFS Register Bit Description 31 16 15 0 Reserved Field 13.4.36 Bit(s) Adaptive IFS Initial Value Description AIFS 15:0 0b Adaptive IFS Value (82544GC/EI only) Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the CSMA/CD transmit function. Normally, this register should be set to 0b.
Register Descriptions Field 13.4.37 Initial Value Bit(s) Description ZERO 3:0 0b Zero Value This field is ignored on write and reads as 0b. TDBAL 31:4 X Transmit Descriptor Base Address Low [31:4] This register indicates lower 32 bits of the start address for the transmit descriptor ring buffer. Transmit Descriptor Base Address High TDBAH (03804h; R/W) This register contains the upper 32 bits of the 64-bit transmit Descriptor base address. Table 13-80.
Register Descriptions 13.4.39 LEN 19:7 0b Descriptor Length. Number of bytes allocated to the transmit descriptor circular buffer. Reserved 31:20 0b Reserved Reads as 0b. Should be written with 0b for future compatibility. Transmit Descriptor Head TDH (03810h; R/W) This register contains the head pointer for the transmit descriptor ring. It holds a value that is an offset from the base, and indicates the in–progress descriptor. It points to a 16-byte datum. Hardware controls this pointer.
Register Descriptions Field 13.4.40 Initial Value Bit(s) Description TDH 15:0 0b Transmit Descriptor Head Reserved 31:16 0b Reserved Reads as 0b. Should be written with 0b for future compatibility. Transmit Descriptor Tail TDT (03818h; R/W) This register contains the tail pointer for the transmit descriptor ring. It holds a value that is an offset from the base, and indicates the location beyond the last descriptor hardware can process.
Register Descriptions Table 13-84. TIDV Register Bit Description 31 16 15 Reserved Field 13.4.42 Initial Value Bit(s) 0 IDV Description IDV 15:0 X Interrupt Delay Value Counts in units of 1.024 µs. A value of 0bis not allowed. Reserved 31:16 0b Reserved Reads as 0b. Should be written to 0b for future compatibility. TX DMA Control (82544GC/EI only) TXDMAC (03000h; R/W) This register controls the transmit DMA pre-fetching and preemption abilities. Table 11-85.
Register Descriptions Table 13-86. TXDCTL Register Bit Description 31 25 LWTHRESH RSV1 1. 23 GRAN 22 21 RSV 16 15 WTHRESH 14 13 RSV 8 7 HTHRESH 6 5 RSV 0 PTHRESH 82544GC/EI only. Field Bit(s) Initial Value Description PTHRESH 5:0 0b Prefetch Threshold Used to control when a pre-fetch of descriptors is considered. This threshold refers to the number of valid, unprocessed transmit descriptors the Ethernet controller has in its on-chip buffer.
Register Descriptions Field Reserved Initial Value Bit(s) 23:22 Description 0b Reserved Reads as 0b. Should be written as 0b for future compatibility. GRAN 24 0b Granularity Set the values of PTHRESH, HTHRESH and WTHRESH in units of cache lines or descriptors (each descriptor is 16 bytes) 1b = Descriptor granularity. 0b = Cache line granularity.
Register Descriptions The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts. However, it might be necessary to ensure that no completed transmit remains unnoticed for too long an interval in order ensure timely release of transmit buffers. This register can be used to ENSURE that a transmit interrupt occurs at some predefined interval after a transmit is completed.
Register Descriptions When performing TCP segmentation, the packet prototype header initially transferred by DMA is stored internally and updated as each packet of the TCP segmentation operation is composed. As data for subsequent TCP segments is DMA’d into the Ethernet controller, the frame header for each segment is dynamically inserted in front of the frame payload data stream prior to being written to the packet buffer.
Register Descriptions 13.4.46 Receive Descriptor Control RXDCTL (02828h; R/W) This register controls the fetching and write-back of receive descriptors. The three threshold values are used to determine when descriptors are read from and written to host memory. The values can be in units of cache lines or descriptors (each descriptor is 16 bytes) based on the GRAN flag.
Register Descriptions Field 13.4.47 Bit(s) Initial Value Description WTHRESH 21:16 1b Write Back Threshold WTHRESH controls the write back of processed receive descriptors. This threshold refers to the number of receive descriptors in the Ethernet controller’s on-chip buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write back occurs only after more than WTHRESH descriptors are available for write back.
Register Descriptions Field PCSS Reserved 1. 2. 322 0b IP Checksum Off-load Enable RXCSUM.IPOFLD is used to enable the IP Checksum offloading feature. If RXCSUM.IPOFLD is set to 1b, the Ethernet controller calculates the IP checksum and indicates a pass/fail indication to software through the Checksum Error bit (CSE) in the ERROR field to the receive descriptor. If both RXCSUM.IPOFLD and RXCSUM.TUOFLD are set, the Checksum Error bit (CSE) is set if either checksum was incorrect. If neither RSCSUM.
Register Descriptions 13.5 Filter Registers This section contains detailed descriptions for those registers associated with the Ethernet controller’s address filter capabilities. 13.5.1 Multicast Table Array MTA[127:0] (05200h-053FCh; R/W) The multicast table array is a way to extend address filtering beyond the 16 perfect in the Receive Address Register (RAR).
Register Descriptions Of the 16 bits, look at bits 11:5, starting from zero. These seven bits corresponds to the row within the MTA table (the MTA has 128 rows which require seven bits to define). In the example, bits 11:5 are 1011110b. This corresponds to row 94. Of these 16 bits, count out the first five bits, again starting from bit zero. These first five bits correspond to the bit within the row (the MTA is 32 bits wide which require five bits to define). In the example this is 01001b.
Register Descriptions 13.5.2 Receive Address Low RAL (05400h + 8*n; R/W) 16 registers contain the lower bits of the 48-bit Ethernet address. All 32 bits are valid. Software can access the High and Low registers as a register pair if it can perform a 64-bit access to the PCI bus. The addresses stored in these registers are used for unicast/multicast address filtering.
Register Descriptions Table 13-91. RAH Register Bit Description 31 30 18 17 AV Reserved Field RAH 0 RAH Description X Receive address High Contains the upper 16 bits of the 48-bit Ethernet address. RAH0 should be used to store the upper 16-bit of the Ethernet controller’s Ethernet MAC address. AS 17:16 X Address Select Selects how the address is to be used in the address filtering.
Register Descriptions Table 13-92. VFTA[127:0] Bit Description 31 0 VLAN Filter Bit Vector Field Bit Vector Initial Value Bit(s) 31:0 Description Double-word wide bit vector specifying 32 bits in the VLAN Filter table. X 13.6 Wakeup Registers 13.6.1 Wakeup Control Register WUC (05800h; R/W) This register is reset any time LAN_PWR_GOOD is set to 0b. When AUX_POWER equals 0b, this register is also reset by de-asserting (rising edge) RST#.
Register Descriptions Field Description APMPME 3 0b Assert PME On APM Wakeup If set to 1b, the Ethernet controller sets the PME_Status bit in the Power Management Control / Status Register (PMCSR) and asserts PME# when APM Wakeup is enabled and the Ethernet controller receives a matching Magic Packet. This field value is loaded from the EEPROM. Note: Not applicable to the 82541ER. Reserved 27:4 0b Reserved Reads as 0b.
Register Descriptions 31 Reserved 1. 2. 3. 20 19 18 17 16 15 FLX3 FLX2 FLX1 FLX0 ITCO1 14 Reserved 8 7 6 5 IPv62 IPv43 ARP 4 3 2 BC MC EX 1 0 MAG LNKC 82541xx and 82547GI/EI only. Not applicable to the 82544GC/EI. IP for the 82544GC/EI. Field Initial Value Description LNKC 0 0b Link Status Change Wakeup Enable. MAG 1 0b Magic Packet Wakeup Enable. EX 2 0b Directed Exact Wakeup Enable. MC 3 0b Directed Multicast Wakeup Enable.
Register Descriptions 31 20 Reserved 1. 2. 19 18 17 16 FLX3 FLX2 FLX1 FLX0 Reserved 8 7 6 5 IPv61 IPv42 ARP 4 3 2 BC MC EX 1 0 MAG LNKC Not applicable to the 82544GC/EI. IP for the 82544GC/EI. Field Bit(s) Initial Value Description LNKC 0 0b Link Status Change. MAG 1 0b Magic Packet Received. EX 2 0b Directed Exact Packet Received The packet’s address matched one of the 16 pre-programmed exact values in the Receive Address registers.
Register Descriptions 13.6.4 IP Address Valid IPAV (5838h; R/W) The IP Address Valid indicates whether the IP addresses in the IP Address Table are valid. The valid bits are reset any time LAN_PWR_GOOD is 0b. When AUX_POWER equals 0b, the valid bits are also reset by deasserting (rising edge) RST#. 31 17 16 v601 Reserved 1. 2. Field 15 4 Reserved 3 2 1 0 V43 V42 V41 V40 V32 V22 V12 V02 Not applicable to the 82544GC/EI. 82544GC/EI only.
Register Descriptions 13.6.5 IPv4 Address Table1 IP4AT (05840h - 05858h; R/W)2 The IPv4 Address Table is used to store the four IP addresses for ARP Request packet and Directed IP packet wakeup for IPv4. Note: This table is not cleared by any reset. DWORD# 31 0 5840h IPV4ADDR01 2 5848h IPV4ADDR1 3 5850h IPV4ADDR2 4 5858h IPV4ADDR3 1. 0 IPA for the 82544GC/EI.
Register Descriptions 13.6.6 IPv6 Address Table1 IP6AT (05880h - 0588Ch; R/W) The IPv6 Address Table is used to store the IPv6 addresses for ARP Request packet and Directed IP packet wakeup for IPv6. Note: This table is not cleared by any reset.
Register Descriptions 13.6.7 Wakeup Packet Length WUPL (05900h; R/W) This register indicates the length of the first wakeup packet received. It is valid if one of the bits in the Wakeup Status Register (WUSR) is set. It can be written for diagnostic purposes and is not cleared by any reset. 31 12 11 Reserved Field LEN 13.6.8 Bit(s) 11:0 0 Length Initial Value Description Length of wakeup packet. (If jumbo frames is enabled and the packet is longer than 2047 bytes this field is 2047.
Register Descriptions Before writing to the Flexible Filter Length Table the driver must first disable the flexible filters by writing 0b’s to the Flexible Filter Enable bits of the Wakeup Filter Control Register (WUFC.FLXn). 31 13.6.
Register Descriptions Field Dword # Address Bit(s) Initial Value Description MASK0 0 9000h 15:0 X Mask for Filter [3:0] for Byte 0 MASK1 2 9008h 15:0 X Mask for Filter [3:0] for Byte 2 MASK2 4 9010h 15:0 X Mask for Filter [3:0] for Byte 3 254 93F8h 15:0 X Mask for Filter [3:0] for Byte 127 ... MASK127 13.6.
Register Descriptions All Statistics registers reset when read. 64-bit registers reset whenever the upper 32 bits are read. In addition, they stick at FFFFh_FFFFh when the maximum value is reached. The Statistics registers are not hardware initialized. Their default value is unknown. Software should read the contents of all registers in order to clear them prior to enabling the receive and transmit channels. Note: 13.7.
Register Descriptions Table 13-94. ALGNERRC Register Bit Description 31 0 AEC 13.7.3 Field Bit(s) Initial Value AEC 31:0 0b Description Alignment error count Symbol Error Count SYMERRS (04008h; R) Counts the number of symbol errors between reads. The count increases for every bad symbol received, whether or not a packet is currently being received and whether or not the link is up. This register only increments in internal SerDes mode (TBI mode for the 82544GC/EI). Table 13-95.
Register Descriptions Table 13-96. RXERRC Register Bit Description 31 0 RXEC 13.7.5 Field Bit(s) Initial Value RXEC 31:0 0b Description RX error count Missed Packets Count MPC (04010h; R) Counts the number of missed packets. Packets are missed when the receive FIFO has insufficient space to store the incoming packet. This can be caused because of too few buffers allocated, or because there is insufficient bandwidth on the PCI bus.
Register Descriptions Table 13-98. SCC Register Bit Description 31 0 SCC 13.7.7 Field Bit(s) Initial Value SCC 31:0 0b Description Number of times a transmit encountered a single collision. Excessive Collisions Count ECOL (04018h; R) When 16 or more collisions have occurred on a packet, this register increments, regardless of the value of collision threshold. If collision threshold is set below 16, this counter won’t increment.
Register Descriptions Table 13-100. MCC Register Bit Description 31 0 MCC 13.7.9 Field Bit(s) Initial Value MCC 31:0 0b Description Number of times a successful transmit encountered multiple collisions. Late Collisions Count LATECOL (04020h; R) Late collisions are collisions that occur after 64-byte time into the transmission of the packet while working in 10-100 Mb/s data rate, and 512 byte time into the transmission of the packet while working in the 1000 Mb/s data rate.
Register Descriptions 13.7.11 Defer Count DC (04030h; R) This register counts defer events. A defer event occurs when the transmitter cannot immediately send a packet due to the medium being busy either because another device is transmitting, the IPG timer has not expired, half-duplex deferral events, reception of XOFF frames, or the link is not up. This register only increments if transmits are enabled. This counter does not increment for streaming transmits that are deferred due to TX IPG. Table 13-103.
Register Descriptions 13.7.13 Sequence Error Count SEC (04038h; R) This register counts sequence error events. The proper sequence of 8b/10b symbols is as follows: idle, start-of-frame (SOF), data, pad (optional), end-of-frame (EOF), fill (optional), idle. Hardware increments this counter for any illegal sequence of delimiters. If the link is not up, this register does not increment. This register is only valid in internal SerDes mode (TBI mode for the 82544GC/ EI). Table 13-105.
Register Descriptions 13.7.15 Receive Length Error Count RLEC (04040h; R) This register counts receive length error events. A length error occurs if an incoming packet passes the filter criteria but is undersized or oversized. Packets less than 64 bytes are undersized. Packets over 1522 bytes are oversized if LongPacketEnable is 0b (RCTL.LPE). If LongPacketEnable (LPE) is 1b, then an incoming packet is considered oversized if it exceeds 16384 bytes.
Register Descriptions 13.7.17 XON Transmitted Count XONTXC (0404Ch; R) This register counts the number of XON packets transmitted. These can be either due to a full queue or due to software initiated action (using TCTL.SWXOFF). This register only increments if transmits are enabled. Table 13-109. XONTXC Register Bit Description 31 0 XONTXC 13.7.18 Field Bit(s) Initial Value XONTXC 31:0 0b Description Number of XON packets transmitted.
Register Descriptions Table 13-111. XOFFTXC Register Bit Description 31 0 XOFFTXC 13.7.20 Field Bit(s) Initial Value XOFFTXC 31:0 0b Description Number of XOFF packets transmitted. FC Received Unsupported Count FCRUC (04058h; R) This register counts the number of unsupported flow control frames that are received.
Register Descriptions Table 13-113. PRC64 Register Bit Description 31 0 PRC64 13.7.22 Field Bit(s) Initial Value PRC64 31:0 0b Description Number of packets received that are 64 bytes in length. Packets Received (65-127 Bytes) Count PRC127 (04060h; R) This register counts the number of good packets received that are 65-127 bytes (from through , inclusively) in length. Packets that are counted in the Missed Packet Count register are not counted in this register.
Register Descriptions Table 13-115. PRC225 Register Bit Description 31 0 PRC255 13.7.24 Field Bit(s) Initial Value PRC255 31:0 0b Description Number of packets received that are 128-255 bytes in length. Packets Received (256-511 Bytes) Count PRC511 (04068h; R) This register counts the number of good packets received that are 256-511 bytes (from through , inclusively) in length.
Register Descriptions Table 13-117. PRC1023 Register Bit Description 31 0 PRC1023 13.7.26 Field Bit(s) Initial Value Description PRC1023 31:0 0b Number of packets received that are 512-1023 bytes in length. Packets Received (1024 to Max Bytes) Count PRC1522 (04070h; R) This register counts the number of good packets received that are from 1024 bytes to the maximum (from through , inclusively) in length.
Register Descriptions Table 13-119. GPRC Register Bit Description 31 0 GPRC 13.7.28 Field Bit(s) Initial Value GPRC 31:0 0b Description Number of good packets received (of any length). Broadcast Packets Received Count BPRC (04078h; R) This register counts the number of good (no errors) broadcast packets received. This register does not count broadcast packets received when the broadcast address filter is disabled. This register only increments if receives are enabled. Table 13-120.
Register Descriptions Table 13-121. MPRC Register Bit Description 31 0 MPRC 13.7.30 Field Bit(s) Initial Value MPRC 31:0 0b Description Number of multicast packets received. Good Packets Transmitted Count GPTC (04080h; R) This register counts the number of good (no errors) packets transmitted. A good transmit packet is considered one that is 64 or more bytes in length (from through , inclusively) in length. This does not include transmitted flow control packets.
Register Descriptions Table 13-123. GORCL and GORCH Register Bit Description 31 0 31 0 GORCH 13.7.32 GORCL Field Bit(s) Initial Value GORCL 31:0 0b Number of good octets received – lower 4 bytes. GORCH 31:0 0b Number of good octets received – upper 4 bytes. Description Good Octets Transmitted Count GOTCL (04090h; R)/ GOTCH (04094; R) These registers make up a 64-bit register that counts the number of good (no errors) octets transmitted.
Register Descriptions This register does not increment when flow control packets are received. Table 13-125. RNBC Register Bit Description 31 0 RNBC Field RNBC 13.7.34 Bit(s) 31:0 Initial Value 0b Description Number of receive no buffer conditions. Receive Undersize Count RUC (040A4h; R) This register counts the number of received frames that passed address filtering, and were less than minimum size (64 bytes from through , inclusively), and had a valid CRC.
Register Descriptions Table 13-127. RFC Register Bit Description 31 0 RFC 13.7.36 Field Bit(s) Initial Value RFC 31:0 0b Description Number of receive fragment errors. Receive Oversize Count ROC (040ACh; R) This register counts the number of received frames with valid CRC field that passed address filtering, and were greater than maximum size. Packets over 1522 bytes are oversized if LongPacketEnable (RCTL.LPE) is 0b.
Register Descriptions Table 13-129. RJC Register Bit Description 31 0 RJC 13.7.38 Field Bit(s) Initial Value RJC 31:0 0b Description Number of receive jabber errors. Management Packets Received Count1 MGTPRC (040B4h; R) This register counts the total number of packets received that pass the management filters as described in the appropriate Total Cost of Ownership (TCO) System Management Bus Interface Application Notes. Management packets include RMCP and ARP packets.
Register Descriptions 13.7.39 Management Packets Dropped Count1 MGTPDC (040B8h; R) This register counts the total number of packets received that pass the management filters as described in the appropriate Total Cost of Ownership (TCO) System Management Bus Interface Application Notes and then are dropped because the management receive FIFO is full or the packet is longer than 200 bytes. Management packets include RMCP and ARP packets. 31 0 MGTPDC Field MGTPDC 13.7.
Register Descriptions All packets received have their octets summed into this register, regardless of their length, whether they are erred, or whether they are flow control packets. This register includes bytes received in a packet from the field through the field, inclusively. This register only increments if receives are enabled. Table 13-130. TORL and TORH Register Bit Descriptions 31 0 31 0 TORH 13.7.
Register Descriptions 13.7.43 Total Packets Received TPR (040D0h; R) This register counts the total number of all packets received. All packets received are counted in this register, regardless of their length, whether they have errors, or whether they are flow control packets. This register only increments if receives are enabled. Table 13-132. TPR Register Bit Description 31 0 TPR Field TPR 13.7.44 Bit(s) 31:0 Initial Value 0b Description Number of all packets received.
Register Descriptions 13.7.45 Packets Transmitted (64 Bytes) Count PTC64 (040D8h; R) This register counts the number of packets transmitted that are exactly 64 bytes (from through , inclusively) in length. Partial packet transmissions (collisions in halfduplex mode) are not included in this register. This register does not include transmitted flow control packets (which are 64 bytes in length). This register only increments if transmits are enabled.
Register Descriptions 13.7.47 Packets Transmitted (128-255 Bytes) Count PTC255 (040E0h; R) This register counts the number of packets transmitted that are 128-255 bytes (from through , inclusively) in length. Partial packet transmissions (collisions in halfduplex mode) are not included in this register. This register only increments if transmits are enabled.
Register Descriptions 13.7.49 Packets Transmitted (512-1023 Bytes) Count PTC1023 (040E8h; R) This register counts the number of packets transmitted that are 512-1023 bytes (from through , inclusively) in length. Partial packet transmissions (collisions in halfduplex mode) are not included in this register. This register only increments if transmits are enabled.
Register Descriptions 13.7.51 Multicast Packets Transmitted Count MPTC (040F0h; R) This register counts the number of multicast packets transmitted. This register does not include flow control packets and increments only if transmits are enabled. Counts clear as well as secure traffic. Table 13-140. MPTC Register Bit Description 31 0 MPTC 13.7.52 Field Bit(s) Initial Value MPTC 31:0 0b Description Number of multicast packets transmitted.
Register Descriptions 13.7.53 TCP Segmentation Context Transmitted Count TSCTC (040F8h; R) This register counts the number of TCP segmentation offload transmissions and increments once the last portion of the TCP segmentation context payload is segmented and loaded as a packet into the Ethernet controller’s on-chip transmit buffer. Note that this is not a measurement of the number of packets sent out (covered by other registers).
Register Descriptions 13.8 Diagnostics Registers The Ethernet controller contains several diagnostic registers. These registers enable software to directly access the contents of the Ethernet controller’s internal Packet Buffer Memory (PBM), also referred to as FIFO space. These registers also give software visibility into what locations in the PBM that the hardware currently considers to be the “head” and “tail” for both transmit and receive operations. 13.8.
Register Descriptions Table 13-143. RDFT Register Bit Description 31 13 12 0 Reserved 13.8.3 FIFO Tail Field Bit(s) Initial Value FIFO Tail 12:0 0b Receive FIFO Tail pointer. Reserved 31:13 0b Reads as 0b. Should be written to 0b for future compatibility. Description Receive Data FIFO Head Saved Register RDFHS (02420h; R/W) This register stores a copy of the Receive Data FIFO Head register in case the internal register needs to be restored.
Register Descriptions Table 13-145. RDFTS Register Bit Description 31 13 12 Reserved 13.8.5 0 FIFO Tail Field Bit(s) Initial Value FIFO Tail 12:0 0b A “saved” value of the Receive FIFO Tail pointer. Reserved 31:13 0b Reads as 0b. Should be written to 0b for future compatibility. Description Receive Data FIFO Packet Count RDFPC (02430h; R/W) This register reflects the number of receive packets that are currently in the Receive FIFO.
Register Descriptions Table 13-147. TDFH Register Bit Description) 31 11 10 Reserved 13.8.7 0 FIFO Head Field Bit(s) Initial Value FIFO Head 10:0 0b Transmit FIFO Head pointer. Reserved 31:11 0b Reads as 0b. Should be written to 0b for future compatibility. Description Transmit Data FIFO Tail Register TDFT (03418h; R/W) This register stores the head of the Ethernet controller’s on–chip transmit data FIFO.
Register Descriptions Table 13-149. TDFHS Register Bit Description 31 13 12 0 Reserved 13.8.9 FIFO Head Field Bit(s) Initial Value FIFO Head 12:0 0b A “saved” value of the Transmit FIFO Head pointer. Reserved 31:13 0b Reads as 0b. Should be written to 0b for future compatibility. Description Transmit Data FIFO Tail Saved Register TDFTS (03428h; R/W) This register stores a copy of the Transmit Data FIFO Tail register in case the internal register needs to be restored.
Register Descriptions Table 13-151. TDFPC Register Bit Description 31 13 12 0 Reserved 13.8.11 FIFO Tail Field Bit(s) Initial Value FIFO Tail 12:0 0b The number of packets to be transmitted that are currently in the TX FIFO. Reserved 31:13 0b Reads as 0b. Should be written to 0b for future compatibility. Description Packet Buffer Memory PBM (10000h - 1FFFCh; R/W) All PBM (FIFO) data is available to diagnostics. Locations can be accessed as 32-bit or 64-bit words.
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General Initialization and Reset Operation General Initialization and Reset Operation 14.1 14 Introduction This section lists all necessary initializations and describes the reset commands for the PCI/PCI-X Family of Gigabit Ethernet Controllers. Note: 14.2 TBI mode is used by the 82544GC/EI. Internal SerDes is used by the 82546GB/EB and 82545GM/EM. Power Up State At power up, the Ethernet controller is not automatically configured by the hardware for normal operation.
General Initialization and Reset Operation • PHY Reset (CTRL.PHY_RST) should be set to 0b. Setting this bit to 1b resets the PHY without accessing the PHY registers. This bit is ignored in internal SerDes mode. • CTRL.ILOS should be set to 0b (not applicable to the 82541xx and 82547GI/EI). • If Flow Control is desired, program the FCAH, FCAL, FCT and FCTTV registers. If not, they should be written with 0b. To enable XON frame transmission, the XON Enable (FCTRL.XONE) bit must be set.
General Initialization and Reset Operation Program the Receive Control (RCTL) register with appropriate values for desired operation to include the following: • Set the receiver Enable (RCTL.EN) bit to 1b for normal operation. However, it is best to leave the Ethernet controller receive logic disabled (RCTL.EN = 0b) until after the receive descriptor ring has been initialized and software is ready to process received packets. • Set the Long Packet Enable (RCTL.
General Initialization and Reset Operation • Configure the Collision Threshold (TCTL.CT) to the desired value. Ethernet standard is 10h. This setting only has meaning in half duplex mode. • Configure the Collision Distance (TCTL.COLD) to its expected value. For full duplex operation, this value should be set to 40h. For gigabit half duplex, this value should be set to 200h. For 10/100 half duplex, this value should be set to 40h.
General Initialization and Reset Operation Note: IPGR1 and IPGR2 are not needed in full duplex, but are easier to always program to the values shown. Table 14-1. Signal Descriptions Signal LOS / LINK Ball Name and Function A10 Loss of Signal (TBI) / Link Indication. Loss of signal (high for lost signal) from the optical transceiver when LINK_MODE equals 11b; active high link indication from PHY in GMII/MII mode.
General Initialization and Reset Operation Signal CRS Ball Name and Function A6 Carrier Sense. TBI: Undefined. GMII / MII: This signal indicates traffic activity on the cable, either incoming or outgoing. This signal is driven by the PHY. CS is not required to transition synchronously with respect to the RX or TX clocks. This signal is ignored in full-duplex mode. Normal Mode: This signal must be connected to VSS except for test mode.
General Initialization and Reset Operation Table 14-2.
General Initialization and Reset Operation Table 14-3. Signal Functions Not Supported Signal Function Ramifications MII Management Interface (PHY Register Access) MDC Management Data Clock MDI/O Management Data I/O No support/access to MII register set. Direct PHY Indications to MAC 14.5.3 FDX PHY-negotiated full/half duplex indication Can limit use to specific known duplex setting.
General Initialization and Reset Operation 14.5.5 Link Setup The following examples are provided as suggestions for configuring common settings between the MAC and an Ethernet controller attached in the GMII/MII mode. • MAC duplex and speed settings forced by software based on resolution of PHY (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.ASDE = don’t care) CTRL.FD Set by software based on reading PHY status register after PHY has autonegotiated a successful link-up. CTRL.
General Initialization and Reset Operation • MAC/PHY duplex and speed settings both forced by software (fully-forced link setup) (CTRL.FRCDPLX = 1b, CTRL.FRCSPD = 1b, CTRL.SLU = 1b) CTRL.FD ...................Set by software to desired full/half duplex operation (must match duplex setting of PHY) CTRL.SLU.................Must be set to 1b by software to enable communications between MAC and PHY. PHY must also be forced/configured to indicate positive link indication (LINK) to the MAC CTRL.RFCE ...........
General Initialization and Reset Operation Once link is achieved by the PHY, software is notified when a Link Status Change (LSC) interrupt is generated by the Ethernet controller. This only occurs if software enabled the LSC bit in the Interrupt Mask Set/Read (MS) Register. 14.7 Reset Operation The following reset signals affect the Ethernet controller in different ways. RST# is the only external signal.
General Initialization and Reset Operation RST#: When asserted, all PCI signals are forced to a high impedance state. Upon deassertion, the Ethernet controller’s internal registers, excluding the following exceptions, are reset. General Registers: Reset to power-on values. Interrupt Registers: Reset to power-on values. Receive Registers: Reset to power-on values (exceptions are the RAH/RAL, MTA, VFTA and RDBAH/RDBAL registers, which are not reset to any preset value.
General Initialization and Reset Operation Default values for certain bits of the Device Control Register must be read out of the EEPROM and appropriately set by software if an EEPROM is used. Global Reset does NOT affect the direction of the software programmable pins. Link_Reset: When LRST (bit 3 of the Device Control register) is written as a logic 1b, the Ethernet controller is forced into a link reset state. When LRST is set to 1b the Auto-Negotiation function is disabled.
General Initialization and Reset Operation Driver accessible Wakeup Status registers are excluded from all resets except for LAN_PWR_GOOD. This includes: • Wakeup Status Register. • Wakeup Packet Length. • Wakeup Packet Memory. Finally, the “Wakeup Context” as defined in the PCI Bus Power Management Interface Specification is reset on LAN_PWR_GOOD, and is also reset on the deassertion of RST# if AUX_POWER = 0b. This includes: • PME_En bit of the Power Management Control/Status Register (PMCSR).
Diagnostics and Testability Diagnostics and Testability 15.1 15 Diagnostics This section explains the registers provided for diagnostic access. These registers enable system level integration and debugging, including the ability to access all internal memories. This information is often critical in determining failure modes and in developing software workarounds. At a diagnostic level, all of the major internal data structures visible to and controllable by software, including all of the FIFO space.
Diagnostics and Testability 15.1.3.1 Internal Loopback This loopback mode internally loops back the transmit to receive path in the PHY, exercising the internal GMII/MII bus. Programming both MAC and PHY is required.
Diagnostics and Testability 15.2.1 EXTEST Instruction This instruction allows testing of off-chip circuitry and board level interconnections. Data is typically loaded onto the latched parallel outputs of the boundary-scan shift register stages using the SAMPLE/PRELOAD instruction prior to selection of the EXTEST instruction. 15.2.2 SAMPLE/PRELOAD Instruction This mandatory instruction allows a snapshot of the normal operation of the component to be taken and examined.
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Appendix (Changes From 82544EI/82544GC) Appendix (Changes From 82544EI/82544GC) A.1 A Introduction This section describes the new features that have been added to the PCI/PCI-X Family of Gigabit Ethernet Controllers from its predecessor, the 82544EI/82544GC and highlights its registers that have been changed. A.2 New Features Following is a list of the new features in the Ethernet controller, along with sections in this manual that describe these features in detail: • Integrated dual-port solution.
Appendix (Changes From 82544EI/82544GC) A.3 Register Changes Table A-1 lists the registers that have been added or changed in the Ethernet controller. Table A-1.
Appendix (82540EP/EM and 82545GM/EM Differences) Appendix (82540EP/EM and 82545GM/EM Differences)B B.1 Introduction This section describes the differences between the 82546GB/EB, the 82540EP/EM and the 82545GM/EM. All three of these Ethernet controllers come from the same family so their register sets are essentially the same. The sections that follow describe the differences between the 82546GB/EB and the 82540EP/EM or 82545GM/EM, and resulting register differences and developer impact. B.
Appendix (82540EP/EM and 82545GM/EM Differences) Note: Though the 82540EP/EM supports devices with up to 512 KB of memory, smaller devices may also be used. Accesses to memory beyond the FLASH device size results in access wrapping as only the lower address bits are utilized by the FLASH. The 82540EP/EM does not provide an interface for performing an “Erase” operation to the serial Flash device. Flash write operations must be performed to an initialized or pre-erased Flash device.
