4538 PMC® T1/E1/J1 Communications Controller Hardware Reference Manual Document No.
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Contents List of Figures Y List of Tables YLL List of Examples
Contents PowerSpan I²O Registers Interrupt Pins and Doorbell Usage PCI to Local Interrupt (ATN) Local to PCI Interrupt (–INTA)
Contents CPM RCCR Reset CHAPTER 3 Programming the Peripherals Overview PowerQUICC II CPM Initialization
Contents In Situ EPLD Programming Optimizing the PCI Bus Utilization Effective Ordering of the PCI Accesses PCI Deadlock Situations
List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 1-16. Figure 1-17. Figure 1-18. Figure 1-19. Figure 1-20. Figure 1-21. Figure 3-1. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. 4538 Structure ....................................................................................................................................
List of Figures vi Interphase Corporation
List of Tables Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 1-7. Table 1-8. Table 1-9. Table 1-10. Table 1-11. Table 1-12. Table 1-13. Table 1-14. Table 1-15. Table 1-16. Table 1-17. Table 1-18. Table 1-19. Table 1-20. Table 1-21. Table 1-22. Table 1-23. Table 1-24. Table 1-25. Table 1-26. Table 1-27. Table 1-28. Table 1-29. Table 1-30. Table 1-31. Table 1-32. Table 1-33. Table 2-1. Table 2-2. Table 2-3. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7.
List of Tables Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. viii J4 TTY Serial Connector ....................................................................................................................... 98 PMC Connector P1 ................................................................................................................................ 98 PMC Connector P2 .......................................................................................
List of Examples ([DPSOH ([DPSOH ([DPSOH ([DPSOH ([DPSOH ([DPSOH ([DPSOH 3RZHU6SDQ ,QWHUUXSW 0DS 5HJLVWHUV ,QLWLDOL]DWLRQ &RGH 5HVHW DQG 5XQ &RPPDQG 5RXWLQHV 3&, WR /RFDO ,QWHUUXSW 5RXWLQHV )URP WKH 3&, 6LGH 5RXWLQHV 5HODWHG WR
List of Examples x Interphase Corporation
Using This Guide Purpose This 4538 Hardware Reference Manual is designed for software developers in Interphase customer organizations who intend to develop embedded software and/or host drivers for the 4538 T1/E1/J1 communications controller. The 4538 is delivered with an Interphase Boot Firmware located in the FLASH memory. This firmware initializes and configures the 4538 hardware at each boot. It also includes built-in self tests and a monitor.
Byte Ordering and Bit Coding Convention Byte Ordering and Bit Coding Convention The PCI bus uses the Little Endian Byte ordering: byte 0 in a 32-bit word is the Least Significant Byte (LSB) from an arithmetic point of view and is noted D(7:0). The PowerPC architecture uses the Big Endian Byte ordering: byte 0 in a 32-bit word is the Most Significant Byte (MSB) from an arithmetic point of view and is noted D(31:24).
CAUTION The Caution icon brings to your attention those items or steps that, if not properly followed, could cause problems in your machine’s configuration or operating system. WARNING The Warning icon alerts you to steps or procedures that could be hazardous to your health, cause permanent damage to the equipment, or impose unpredictable results on the surrounding environment. Text Conventions The following conventions are used in this manual. Computer-generated text is shown in typewriter font.
Checking and Downloading from the Interphase WWW/FTP Site Checking and Downloading from the Interphase WWW/FTP Site The latest production software drivers, firmware, and documentation (in Adobe Acrobat PDF or text format) for our current products are available on our WWW / FTP site. Interphase recommends our customers visit the web site often to verify that they have the latest version of driver, firmware, or documentation. WWW Method 1. Access the following web page: http://www.iphase.com 2.
operating system subdirectories. In these cases, you must choose the proper bus and operating system by typing cd for the appropriate subdirectories. 8. To download one or more files to your local directory, enter get 9.
Checking and Downloading from the Interphase WWW/FTP Site xvi Interphase Corporation
1Hardware Description 1 Overview The Interphase 4538 PMC E1/T1/J1 Communications Controller is a network interface PCI Mezzanine Card (PMC) equipped with four software-selectable T1/E1/J1 interfaces (two are provided on the front panel). The 4538 board is intended for 2G and 3G wireless networks, Internet access, and Advanced Intelligent Network (AIN) applications. This chapter provides the functional specification of the 4538.
The PowerQUICC II 4538 Hardware Structure Figure 1-1 shows the 4538 hardware structure: (WKHUQHW 0,, 7UDQVFHLYHU 'HYHORSPHQW SRUW 3 3 3&, %XV 03& [ %XV 5- - )UDPHU /LQH , ) 5- - ( 7 - )UDPHU ELWV 0% .E 6HULDO 6'5$0 - /LQH , ) )UDPHUV 3 -$&. )UDPHU 7'0 PX[ 5- - 77< 56 60& 76$ 3RZHU63$1 3&, %ULGJH /LQH , ) ( - 7 0% )ODVK )UDPHU ((3520 Figure 1-1.
Chapter 1: Hardware Description • Three Fast Serial Communications Controllers (FCCs). One is used to control the Ethernet Media-Independent Interface (MII).
The PowerQUICC II Once all the resets are de-asserted, the PowerQUICC II boots using its 8-bit FLASH device. The MPC8260 can control the reset of the various communication peripherals through certain CPM I/O ports. When the PowerQUICC II is in reset state, and until it configures these I/O ports as outputs, these reset signals are activated. System Clocks The MPC8260 gets its reference clock in its CLOCKIN input pin from a 65.536 MHz reference oscillator.
Chapter 1: Hardware Description local processor can also be cachable. The peripherals cannot be cachable. The area of SDRAM memory used for the transfer of data cannot be cachable either, because it can be modified by elements other than the PowerQUICC II, such as the PowerSpan DMA. In order to simultaneously support cachable and non cachable areas in the SDRAM memories, they are mapped twice in the local space. One mapping area will be defined as cachable and the other will be defined as non cachable.
The PowerQUICC II 0x0000 0000 '%$7 [ EXV 0% 6'5$0 &6 ,%$7 FDFKDEOH 0x03FF FFFF 0xF002 0000 0xF002 FFFF 3RZHU63$1 5HJ 0xF008 0000 0xF008 FFFF 4XDG)$/& QRW FDFKDEOH .% QRW FDFKDEOH .% &6 0x8000 0000 [ EXV 6'5$0 0% GXSOLFDWHG &6 '%$7 QRW FDFKDEOH 0x83FF FFFF 0x8FFF FFFF 0xC000 0000 /RFDO WR 3&, 0% '%$7 ZLQGRZ 0xCFFF FFFF QRW FDFKDEOH 0xFF00_0000 0xFF01_FFFF 03& ,QWHUQDO 5HJLVWHUV 03& 5HJLVWHUV QRW FDFKDEOH .
Chapter 1: Hardware Description NOTE Accesses from the CPM and the PowerSpan cannot go through the Memory Management Unit (MMU), unlike the core accesses. Therefore, the CPM and PowerSpan must use the physical addresses when accessing the SDRAMs (most significant bit = 0). Accesses to 0x8000 0000 will not address the SDRAMs. Interrupts The PCI bridge PowerSpan and the communication peripherals generate interrupt requests to the PowerQUICC II. These interrupts are level sensitive, active low. Table 1-2.
The PowerQUICC II Communication Processor Module (CPM) I/O Ports The CPM part of the PowerQUICC II provides several communication functions. These functions use multi-mode pins that are grouped in four I/O ports: Port A, B, C, and D. The 4538 communications controller uses these ports as shown in the following tables: 7DEOH CPM Port A Usage &30 , 2 3RUW 3LQ &RQILJXUDWLRQ 'LU 8VDJH 3$ 2XWSXW 2 &20&/.
Chapter 1: Hardware Description 7DEOH CPM Port C Usage &30 , 2 3RUW 3LQ &RQILJXUDWLRQ 'LU 8VDJH 3& 2XWSXW 2 8QXVHG 3& 2XWSXW 2 4XDG)$/& UHVHW DFWLYH 3& 2XWSXW 2 8QXVHG 3& &/. , )DVW (WKHUQHW 7[ &ORFN 3& &/. , 7'0G 7'0E &ORFN 3& &/. , )DVW (WKHUQHW 5[ &ORFN 3& &/.
The PowerQUICC II Table 1-7.
Chapter 1: Hardware Description The two first TDM busses of each serial interface are connected to the four TDM busses of the QuadFALC. The two others TDM busses of each serial interface are used in “pass through mode”. The TDM busses are at a bit rate of 2.048 Mb/s or 8.192 Mb/s. Bank of Clocks The PowerQUICC II CPM features a bank of clocks that can be selected independently for each device used. However, the choice for each device is limited.
The PowerQUICC II Table 1-12. Ethernet Signals on the CPM (cont) Ethernet Signal CPM I/O Port Dir Description )(B&2/ 3% , &ROOLVLRQ 'HWHFW )(B7;B(1 3% 2 7UDQVPLW (QDEOH )(B7;B(5 3% 2 7UDQVPLW (UURU )(B5;B(5 3% , 5HFHLYH (UURU )(B5;B'9 3% , 5HFHLYH 'DWD 9DOLG )(B0'& 3& 2 0DQDJHPHQW 'DWD &ORFN )(B0',2 3& , 2 0DQDJHPHQW 'DWD , 2 )(B7;B&/. 3& , 7UDQVPLW FORFN )(B5;B&/.
Chapter 1: Hardware Description * * 5 5 &38 /(' &38 /(' &38 /(' &38 /(' Figure 1-3. Board CPU_LEDs Table 1-14.
The PCI Bridge The PowerSpan internal register set can be split into six different functional groups: • PCI configuration registers (these registers, defined by the PCI specification, can be accessed in the standard PCI configuration space or in the local PowerSpan internal registers space) • PCI registers • Processor bus registers • DMA registers • Miscellaneous registers (Mailboxes, Doorbells, Interrupts, Semaphores) • I²O messaging registers The details of the PowerSpan registers can be found by consult
Chapter 1: Hardware Description Table 1-15.
The PCI Bridge Table 1-16. PowerSpan PCI Registers (cont) Offset Register Description [ 3 B$5%B&75/ 3&, %XV $UELWHU &RQWURO 5HJLVWHU PowerSpan Processor Bus Registers These registers are used to define the parameters of the local to PCI windows. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000). Table 1-17.
Chapter 1: Hardware Description PowerSpan DMA Registers These registers are used to control the four bidirectional DMA engines provided in the PowerSpan. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000). Table 1-18.
The PCI Bridge PowerSpan Miscellaneous Registers This group of registers includes several configuration registers for the interrupt functions, as well as various runtime registers: mailboxes, doorbells, interrupt control/status, and semaphores. They are mapped in the PCI memory space (base address defined in PCI configuration register 0x14 PCIBAR1) and in the local space for the local processor (base address 0xF0020000). Table 1-19.
Chapter 1: Hardware Description PowerSpan I²O Registers The PowerSpan includes I²O messaging queues controlled by several registers. These registers are mapped in two places in the PCI memory space: at the base address defined in the PCI configuration register 0x10 PCIBAR0 and in the PowerSpan internal register space (base address defined in PCI configuration register 0x14 PCIBAR1). They are also mapped in the local space for the local processor (base address 0xF0020000). Table 1-20.
The PCI Bridge Interrupt pins –INT1 to –INT4 are configured as output ports and conventionally associated with doorbell bits DB3 to DB6 in the PowerSpan. Each doorbell bit, when set, will activate its corresponding interrupt pin (level = 0), and when reset will deactivate it (level =1). Interrupt pin –INT5 is used as an input. Its state can be read in the PowerSpan Interrupt status register. As an interrupt source, it was decided not to map it to any interrupt output, so it will not generate interrupts.
Chapter 1: Hardware Description Local to PCI Interrupt (–INTA) The PowerQUICC II can generate an interrupt toward the PCI Host by setting a doorbell bit. Conventionally, doorbell bit 0 has been dedicated to this task, and has been associated with the PCI interrupt pin –INTA in the PowerSpan Interrupt Map registers.
The PCI Bridge NOTE A PowerSpan PCI-to-Local window must have been enabled in the I²C serial EEPROM, in order to allow the CompactPCI host to detect it at system power-on or after the “Hot Swap insertion” of the board and to map it in the PCI space. The corresponding PowerSpan register “PCI Target Image Control Register” must also have been initialized with the “Image Enable” bit set (IMG_EN=1) and the address translation mechanism enabled (TA_EN=1).
Chapter 1: Hardware Description /RFDO 0HPRU\ 6SDFH 3&, 0HPRU\ 6SDFH [ 3 B7, B7$''5 3&, %$5 /RFDO DGGUHVV 3&, DGGUHVV 3&, %$5 /RFDO $GGUHVV 3 B7, B7$''5 0% VHW LQ 3 B7, B&7/ 3&, %$5 0% 3 B7, B7$''5 VHW LQ 3 B7, B&7/ [)))))))) /RFDO $GGUHVV EXLOGLQJ H[DPSOH ZLWK 3&, 7DUJHW ,PDJH 3&, %$5 6DPH YDOXH 3&, DGGUHVV 3 B7, B7$''5 /RFDO DGGUHVV :LQGRZ VL]H VHW LQ 3 B7, B&7/ %6 Figure 1-4.
The PCI Bridge dual port RAM, the QuadFALC framers, and the IMA device. (the processor must have its chip selects programmed). The local space mapping is the same as when accessed by the processor (see PCI Local Space Mapping on page 5). It is not possible to have access to the entire FLASH device when the processor is running, because the FLASH device is an 8-bit data bus device connected to the 64-bit-only local bus of the PowerSpan. Only bytes modulo 8 are reachable.
Chapter 1: Hardware Description On the 4538 board, the serial EEPROM content disables the windows. By default, no Local to PCI window is enabled. It is not recommended using these windows for transfers from or to the PCI local space, because this mechanism can result in bad performance, depending on the other PCI devices tied to the PCI bus. The local base address of each window is defined in PowerSpan internal register PB_SIx_BADDR.
The PCI Bridge 3&, , 2 6SDFH RU 3&, 0HPRU\ 6SDFH /RFDO 0HPRU\ 6SDFH [ 3%B6,[B7$''5 3%B6,[B%$''5 /RFDO DGGUHVV 6L]H VHW LQ %6 ILHOG RI 3%B6,[B&7/ [)))))))) /RFDO $GGUHVV EXLOGLQJ H[DPSOH ZLWK 3&, 7DUJHW ,PDJH 3%B6,[B%$''5 6DPH YDOXH /RFDO DGGUHVV 3%B6,[B7$''5 3&, DGGUHVV :LQGRZ VL]H VHW LQ 3%B6,[B&7/ %6 Figure 1-5.
Chapter 1: Hardware Description These devices keep their programming during power off. So the EPLD should normally be already programmed and the normal user should not be aware of its programming. The EPLDs are in a daisy-chain configuration, which enables all of them to be programmed at once. They can be programmed in-situ by the PCI host, using some PowerSpan interrupts as I/O pins.
The PCI Bridge Table 1-24. Hardware Configuration Register Field Descriptions Field Description MPC_ID Microprocessor identifier: 0000: MPC8260ZU200, 200/133/66MHz, rev A.1 0001: MPC8260ZU133, 133/133/66MHz, rev A.1 0010: MPC8260ZU200, 200/133/66MHz, rev B.
Chapter 1: Hardware Description Vital Product Data (VPD) No VPD has been defined for the 4538. Interphase-Specific Production Data and Boot Monitor Parameters Additional information concerning Interphase-specific Production Data and Boot Monitor parameters are provided in the 4538 Built-In Self Test and Monitor Manual. The FLASH EEPROM Boot Memory The boot memory is a 4Mx8 AMD 29LV033 FLASH EEPROM device, placed in the 60x bus byte lane 0.
The QuadFALC T1/E1/J1 Framer Table 1-25. FLASH EEPROM Mapping (cont) FLASH Addr 1st MAP 2nd MAP Size Description 9DOXHV GHSHQG RQ %RRW )LUPZDUH VL]H ZKLFK YDU\ IURP RQH YHUVLRQ WR DQRWKHU ± XVH WKH 021,725 ,1)2 FRPPDQG WR GLVSOD\ WKH DFWXDO VL]H The FLASH device is normally controlled by the PowerQUICC II memory controller unit using chip-select signal CS0. The PowerQUICC II can read and re-program the FLASH using the AMD algorithms.
Chapter 1: Hardware Description The QuadFALC includes a flexible clock unit that uses a clock supplied on its MCLK pin. The QuadFALC MCLK input is connected to a 12.500 MHz +/-20ppm fixed frequency (CPM BRG6) used by the internal DPLL. As a result, the GCM registers must be programmed with the following values: Table 1-26. GCM Register Programming (MCLK=12.
The QuadFALC T1/E1/J1 Framer For each line x, the QuadFALC provides four transmit multifunction ports (XPA_x, XPB_x, XPC_x and XPD_x) and four receive multifunction ports (RPA_x, RPB_x, RPC_x and RPD_x). The tables below indicate how they are used on the 4538 (The RPD port is detailed for each port, since its use differs from one port to another). Table 1-28.
Chapter 1: Hardware Description Each line of the QuadFALC framers can be configured independently in Line Termination mode (LT) or in Network Termination mode (NT). In the LT mode, the QuadFALC is in slave mode and synchronizes on the lines. In the NT mode, the QuadFALC is in master mode and synchronizes on a reference signal provided through connector P4 or on a free running internal frequency. On the front access board, the framers 1 and 2 are tied respectively to J1 and J2 connectors.
TDM Bus Configurations TDM Bus Configurations General The TDM bus general structures are described in Figure 1-6 for the general bus structure and in Figure 1-7 and Figure 1-8 for the general clock structure. This general structure allows three basic configurations that can each have several variants. The configurations are: Direct Mode: The QuadFALC TDM busses are directly tied to the MPC8260. Two variants exist: • Multiplex Direct Mode with one multiplexed TDM bus for the four framers.
Chapter 1: Hardware Description 6:02'(B1 3 ',+ '2+ 6:02'(B1 ',+ '2+ 6:02'(B1 03& 7'0D 7'0F 7'0E 7'0G 7'0D 7'0F 7'0E 7'0G 5; 3(% 7; 5; 5'2B ;',B 6:02'(B1 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; Figure 1-6.
TDM Bus Configurations &.,+ )6,+ &.2+ 6:02'(B1 )62+ 3 6:02'(B1 6<1& )6& / 5&/. &/. 3& 6:02'(B1 3$ '&2 5 / 56<1& 3(% )5$0(5 B '3// 5&/. /LQH 5&/. 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3% ;&/. '&2 ; / 7&/. 7UDQVPLW 6\VWHP &ORFN 6&/.
Chapter 1: Hardware Description )67'0 B1 &.7'0 &20&/.B1 3(% / 5&/. &/. '3// 5&/. /LQH 3& )5$0(5 B 6<1& '&2 5 5&/. / 56<1& 3' 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3' ;&/. '&2 ; / 7&/. 6&/.
TDM Bus Configurations Multiplex Direct Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 1. In multiplex direct mode, the four framers have the same rhythm. The QuadFALC system interface is in multiplex mode; the first QuadFALC TDM bus is directly tied to the CPM TDM bus TDMa1. The TDM bus clock and the frame synchronization signal are provided by the QuadFALC. In NT mode, the QuadFALC can synchronize on an external network reference clock provided on connector P4.
Chapter 1: Hardware Description NOTE TDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must be tristated. 6:02'(B1 3 ',+ '2+ 6:02'(B1 ',+ '2+ 6:02'(B1 03& 7'0D 7'0F 7'0E 7'0G 7'0D 7'0F 7'0E 7'0G 5; 3(% 5'2B 7; 5; ;',B 6:02'(B1 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; Figure 1-9.
TDM Bus Configurations &.,+ )6,+ &.2+ 6:02'(B1 )62+ 3 6:02'(B1 6<1& )6& / 5&/. &/. 3& 6:02'(B1 5&/. 3$ '&2 5 / 56<1& 3(% )5$0(5 B '3// 5&/. /LQH 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3% ;&/. '&2 ; / 7&/. 6&/.
Chapter 1: Hardware Description )67'0 B1 &.7'0 &20&/.B1 3(% / 5&/. &/. '3// 5&/. /LQH 3& )5$0(5 B 6<1& '&2 5 5&/. / 56<1& 3' 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3' ;&/. '&2 ; / 7&/. 7UDQVPLW 6\VWHP &ORFN 6&/.
TDM Bus Configurations Independent Direct Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 1. In independent direct mode, each framer can have its own rhythm. Each QuadFALC TDM bus is directly tied to a CPM TDM bus and has its own clock and frame synchronization signal provided by the QuadFALC. In NT mode, each framer can synchronize on an external network reference clock provided on connector P4. Figure 1-12, Figure 1-13, and Figure 1-14 show the specific implementation of this mode.
Chapter 1: Hardware Description Table 1-31. TDM and Synchronization Signals in Independent Direct Mode (cont) 2XWSXW ,QSXW V 'HVFULSWLRQ 6&/.5 4XDG)$/& 7'0E B/ 5&/. 0+] GHMLWWHUHG 5HFHLYH 6\VWHP &ORFN &05 ,56& JHQHUDWHG E\ WKH '&2 5 FLUFXLW RXWSXW RQ 6&/.
TDM Bus Configurations Table 1-31. TDM and Synchronization Signals in Independent Direct Mode (cont) 2XWSXW ,QSXW V 'HVFULSWLRQ 6&/.5 4XDG)$/& 7'0E B/ 5&/. 0+] GHMLWWHUHG 5HFHLYH 6\VWHP &ORFN &05 ,56& JHQHUDWHG E\ WKH '&2 5 FLUFXLW RXWSXW RQ 6&/.
Chapter 1: Hardware Description 6:02'(B1 3 ',+ '2+ 6:02'(B1 ',+ '2+ 6:02'(B1 03& 7'0D 5; 7; 5'2B ;',B 6:02'(B1 7'0F 7'0E 3(% 5; 5'2B 7; ;',B 5; 5'2B 7; ;',B 5; 5'2B 7; ;',B 7'0G 7'0D 7'0F 7'0E 7'0G Figure 1-12.
TDM Bus Configurations &.,+ )6,+ &.2+ 6:02'(B1 )62+ 3 6:02'(B1 6<1& )6& / 5&/. &/. 3& 6:02'(B1 3$ '&2 5 / 56<1& 3(% )5$0(5 B '3// 5&/. /LQH 5&/. 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3% ;&/. '&2 ; / 7&/. 7UDQVPLW 6\VWHP &ORFN 6&/.
Chapter 1: Hardware Description )67'0 B1 &.7'0 &20&/.B1 3(% / 5&/. &/. '3// 5&/. /LQH 3& )5$0(5 B 6<1& '&2 5 5&/. / 56<1& 3' 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3' ;&/. '&2 ; / 7&/. 6&/.
TDM Bus Configurations Switched Mode In this mode, PA(7) = SWMODE_N = 0 and PA(0) = COMCLK_N = 1. In switched mode, the QuadFALC multiplexed TDM bus is tied to the first TDM bus on P4. The second TDM bus on P4 is tied to the MPC8260. The TDM busses clock and frame synchronization signals are provided by connector P4. In NT mode, the QuadFALC can synchronize on an external network reference clock provided on P4. Figure 1-15, Figure 1-16 and Figure 1-17 show the specific implementation of this mode.
Chapter 1: Hardware Description NOTE TDMb1, TDMc1, TDMd1, TDMa2, TDMb2, TDMc2 and TDMd2 signals are not used and must be tristated. 6:02'(B1 3 ',+ '2+ 6:02'(B1 ',+ '2+ 6:02'(B1 03& 7'0D 7'0F 7'0E 7'0G 7'0D 7'0F 7'0E 7'0G 5; 3(% 5'2B 7; 5; ;',B 6:02'(B1 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; Figure 1-15.
TDM Bus Configurations &.,+ )6,+ &.2+ 6:02'(B1 )62+ 3 6:02'(B1 6<1& )6& / 5&/. &/. 3& 3$ '&2 5 / 56<1& 3(% )5$0(5 B '3// 5&/. /LQH 6:02'(B1 5&/. 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3% ;&/. '&2 ; / 7&/. 7UDQVPLW 6\VWHP &ORFN 6&/.
Chapter 1: Hardware Description )67'0 B1 &.7'0 &20&/.B1 3(% / 5&/. &/. '3// 5&/. /LQH 3& )5$0(5 B 6<1& '&2 5 5&/. / 56<1& 3' 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3' ;&/. '&2 ; / 7&/. 6&/.
TDM Bus Configurations Pass-Through Mode In this mode, PA(7) = SWMODE_N = 1 and PA(0) = COMCLK_N = 0. Pass through is possible from framer 1 to framer 2 and vice versa and from framer 3 to framer 4 and vice versa. The four framers have the same rhythm (COMCLK_N = 0). In framer 1 to framer 2 pass-through mode, the first framer is tied to the network in LT mode.
Chapter 1: Hardware Description Table 1-33. TDM and Synchronization Signals in Pass Through Mode (cont) 2XWSXW ,QSXW V 'HVFULSWLRQ )6& 4XDG)$/& 53$ ;3$ 53$ ;3$ 53$ ;3$ 53$ ;3$ 7'0D B/ 56<1& 7'0E B/ 56<1& 7'0F B/ 56<1& 7'0G B/ 56<1& 7'0D B/ 56<1& 7'0E B/ 56<1& 7'0F B/ 56<1& 7'0G B/ 56<1& .
TDM Bus Configurations 6:02'(B1 3 ',+ '2+ 6:02'(B1 ',+ '2+ 6:02'(B1 03& 7'0D 7'0F 7'0E 7'0G 7'0D 7'0F 7'0E 7'0G 5; 3(% 7; 5; 23(1 '5$,1V 5'2B ;',B 6:02'(B1 7; 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 23(1 '5$,1V 7; 5; 5'2B 7; ;',B 5; 7; Figure 1-18.
Chapter 1: Hardware Description 6:02'(B1 3 ',+ '2+ 6:02'(B1 ',+ '2+ 6:02'(B1 03& 7'0D 7'0F 7'0E 7'0G 7'0D 7'0F 7'0E 7'0G 5; 3(% 7; 5; 7; 5'2B ;',B 6:02'(B1 23(1 '5$,1V 5; 5'2B 7; ;',B 5; 7; 5; 5'2B 7; ;',B 5; 7; 23(1 '5$,1V 5; 5'2B 7; ;',B 5; 7; Figure 1-19.
TDM Bus Configurations &.,+ )6,+ &.2+ 6:02'(B1 )62+ 3 6:02'(B1 6<1& )6& / 5&/. &/. 3& 3$ '&2 5 / 56<1& 3(% )5$0(5 B '3// 5&/. /LQH 6:02'(B1 5&/. 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3% ;&/. '&2 ; / 7&/. 6&/.
Chapter 1: Hardware Description )67'0 B1 &.7'0 &20&/.B1 3(% / 5&/. &/. '3// 5&/. /LQH 3& )5$0(5 B 6<1& '&2 5 5&/. / 56<1& 3' 3& &53 6&/.5 5HFHLYH 6\VWHP &ORFN / 7&/. &05 ,56& / 76<1& 3& &653 3& 53& 6<35 7'0B$ 53$ 5)0 5HF )UDPH 6\QF 3XOVH &05 ,563 3& 53& / 5&/. 5&/. / 56<1& 3' ;&/. '&2 ; / 7&/. 6&/.
TDM Bus Configurations 58 Interphase Corporation
24538 Power-Up Initialization 2 Overview After power-up, the STARTUP code is executed. This code is written entirely in assembly language and is the entry point after a power-up or a reset exception. STARTUP configures the PowerQUICC II and several other critical hardware elements such as the SDRAM memories. Once STARTUP is executed, code written in a high-level language such as “C” is executed. This chapter describes this STARTUP initialization.
PowerSpan Initialization • PWRUP_BOOT=0: The PowerQUICC II boots locally (not through PCI) • PWRUP_DEBUG_EN=0:Disable debug mode • PWRUP_BYPASS_EN=0:Disable PLL bypass PowerSpan Register Initialization Through the I²C Serial EEPROM Table 2-1 provides the PowerSpan Register initialization values stored in the Serial EEPROM. Refer to PowerSpan documentation, section EEPROM Loading for detailed mapping between EEPROM addresses and PowerSpan registers. . Table 2-1.
Chapter 2: 4538 Power-Up Initialization Table 2-1. PowerSpan Register Initialization Values in the Serial EEPROM (cont) EEPROM Address Initialization Value [ ± [ ) [ Description 5HVHUYHG Other PowerSpan Initializations It is necessary to initialize the PowerSpan Interrupt Map registers in a specific way, in order to use the interrupt pins as specified for the 4538. This can be done by the local processor during its boot and/or by the PCI host.
PowerQUICC II Hardware Configuration Word Example 2-1.
Chapter 2: 4538 Power-Up Initialization • MMR =11: External bus requests are masked (PQ2 is the boot master) • LBPC = 00: Local bus enabled • APPC = 10: Address parity pins used for bank select • CS10PC =01: –CS10/–BCTL1 used as –BCTL1 • MODCK_H =0101: PLL multiplication factors: with MODCK[1:3]=111, Bus @66, CPM @133, Core @200 MHz PowerQUICC II Initializations After a power-up or a reset exception, the PowerQUICC II must initialize itself and adapt its System Interface Unit (SIU) to the 4538 har
PowerQUICC II Initializations • LETM = 1: Enable Local Extended Transfer Mode • NPQM = 111: Non PowerQUICC II master connected • EXDD = 0: External Master Delay not disabled • ISPS = 0: Internal Space Port Size = 64 bits The resulting register value is BCR=0xA01C0000. System Protection Control Register (SYPCR) This register controls the software watchdog. It can be read at any time but can be written only once after system reset.
Chapter 2: 4538 Power-Up Initialization • APPC = 00: Address Parity pins used as local bus • CS10PC = 01: –CS10/–BCTL1 used as –BCTL1 • BCTLC = 01: –BCTL0 used as R/–W and –BCTL1 used as –OE • MMR = 11: MMR = 00: External bus requests initially masked at boot, then No bus request masking once booted • LPBSE = 0: LBPS/LGPL4 functions as LGPL4 The resulting register value is SIUMCR=0x4205C000.
PowerQUICC II Initializations • Refresh the SDRAM eight times (OP=001) • Write the SDRAM Mode register (OP=011). For the main SDRAM placed on the 60x bus, the row/column address multiplexing is done externally, so the mode register value must be coded in the column address of the dummy access following the PSDMR programming. • Reset the xDMR register OP field for normal operation (OP=000).
Chapter 2: 4538 Power-Up Initialization The instruction and data caches are enabled through bits ICE and DCE of register HID0 respectively. The setting of ICE bit must be preceded by an isync instruction. The setting of DCE bit must be preceded by a sync instruction. Communication Processor Module Initialization I/O Port Initialization The CPM I/O ports have to be configured according to their usage (see Communication Processor Module (CPM) I/O Ports on page 8).
PowerQUICC II Initializations 68 Interphase Corporation
3Programming the Peripherals 3 Overview This chapter provides information specific to the 4538 board for peripheral programming. Its initial purpose is not to detail how to program the peripherals themselves, for which the developers should refer to the manufacturers data sheets. However, for tricky peripherals, such as T1/E1/J1 framers, some important register programming is detailed.
PowerQUICC II CPM Initialization • RFSDx = 01: Receive frame sync delay for TDMa. 01 for 1 clock delay. • DSCx = 0: Double speed clock for TDMa. 0 means the channel clock rate is equal to the data clock. • CTRx = 1: Common receive and transmit pin clocks for TDMa. 1 means Rx and Tx clocks are common. • SLx = 1: Sync level for TDMa. 1 means sync active level is 0. • CEx = 1: Clock edge for TDMa. When DSCx = 1, data sent on the falling edge and received on the rising edge.
Chapter 3: Programming the Peripherals TDM Busses in Pass-Through Mode According to the TDM busses configuration (VHH 7'0 %XV &RQILJXUDWLRQV on page 34), the SIxAMR, SixBMR, SIxCMR, and SIxDMR registers must be set as follows (x=1 for line 1 to 2 and line 2 to 1, x=2 for line 3 to 4 and line 4 to 3): SIxCMR and SIxDMR • Reserved = 0: This bit should be cleared. • SADx = 000: Starting bank address for the RAM of TDMs. 010 for second bank, first 32 entries. • SDMx = 01: SI Diagnostic Mode for TDMs.
PowerQUICC II CPM Initialization Final Result of SIxAMR (line 1 to 2 and line 3 to 4) and SIxBMR (line 2 to 1 and line 4 to 3) registers is 0x0169. NOTE When a TDM is not used, it is not necessary to initialize the corresponding SIxMR register.
Chapter 3: Programming the Peripherals Clocks and Baud-Rate Generators Introduction The CPM contains eight independent, identical, Baud-Rate Generators (BRGs) that can be used with the FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. In addition, the output of a BRG can be routed to a pin to be used externally.
PowerQUICC II CPM Initialization MCCF1 register initialization: • Group 1 = 00: Group 1 (MCC channels 0-31) is used by TDMa1 • Group 2 = 00: Group 2 (MCC channels 32-63) is used by TDMa1 • Group 3 = 00: Group 3 (MCC channels 64-95) is used by TDMa1 • Group 4 = 00: Group 4 (MCC channels 96-127) is used by TDMa1 Final Result of MCCF1 register is 0x00.
Chapter 3: Programming the Peripherals T1/E1/J1 Framer Initialization Introduction This section details the QuadFALC register initialization, assuming that for non-specified registers, the initialization is the default value (which is generally 0x00). 4538 Boot Firmware sources provides routines to initialize the framers in T1/J1 or E1 mode. Developers should to refer to them. See Boot Firmware sources: tst\c\qfalc.
T1/E1/J1 Framer Initialization Multiplexed Direct Mode In multiplex direct mode, the four framers have the same rhythm. SWMODE_N = 1 and COMCLK_N = 1. System Interface QuadFALC is connected to the CPM through an 8 MHz stream. This stream is the concatenation of four 2 MHz streams, corresponding to the four T1/E1/J1 lines. These four streams are mapped into this 8 MHz stream in an interleaved manner. This interleaved organization is extended to all the 8 MHz streams.
Chapter 3: Programming the Peripherals NOTE For T1/J1 applications, the mapping of the receive 24 line time slots over the 32 available on the system interface is configurable with FMR1.CTM bit. In 4538 Boot firmware, the choice is to select ‘Channel translation mode 1’, by setting FRM1.CTM bit to 1: on reception, the 24 line time slots are contiguously mapped before they are interleaved on the system bus. The same mapping occurs on transmission. Table 3-2.
T1/E1/J1 Framer Initialization SEC/FSC Configuration The SEC/FSC signal of the QuadFALC is connected to CPM and is used for the TDM frame synchronization clock (8 KHz synchronization pulse generated by one of the four DCORs). It must be configured as an FSC output by setting GPC1.CSFP1 to 1. Bit GPC1.CSFP0 allows selecting the active level (low or high). When using the pairing feature, FSC source must match an active channel as for RCLK1: the source is selected with GPC1.FSS1 and GPC1.FSS0 bits.
Chapter 3: Programming the Peripherals RCLK1 is one of the four channels’ internally-generated receive route clocks (RCLK) of a QuadFALC: the channel selection is set with GPC1.R1S1 and GPC1.R1S0 bits – when using RCLK1 for synchronizing the TDM SIxRAM, an active channel should be selected. On each channel, program CMR1.RS1=1 and CMR1.RS0=0: the advantage would be to have RCLK1 at 2.
T1/E1/J1 Framer Initialization RCLK1 Configuration as TDM bus clock 8 KHz synchronization pulse generated by the internal DCO1-R circuit, synchronized to the lines and provided to P4. SEC/FSC Configuration Dejittered clock generated by the internal DCO1-R circuit, synchronized to the lines and provided to P4. Pass-Through Mode In multiplex direct mode, the four framers have the same rhythm. SWMODE_N = 1 and COMCLK_N = 0.
Chapter 3: Programming the Peripherals not go to a continuous level, but is the free running frequency of DCO-R. Since DCO-R is used, program CMR1.DRSS1 and CMR.DRSS0 bits as shown in Table 3-3 to select the reference source for the DCO-R circuit SEC/FSC Configuration The SEC/FSC signal of the QuadFALC is connected to CPM and is used for the TDM frame synchronization clock (8 KHz synchronization pulse generated by one of the four DCO-R). It must be configured as an FSC output by setting GPC1.CSFP1 to 1.
T1/E1/J1 Framer Initialization Framing and Line Coding Initialization Common Initialization Table 3-4.
Chapter 3: Programming the Peripherals E1 Non-CRC4 Specific Initialization Table 3-7. E1 Non-CRC4 Specific Initialization Register Bit Value Comment )05 ;)6 7UDQVPLW GRXEOH IUDPH IRUPDW )05 5)6 5HFHLYH GRXEOH IUDPH IRUPDW E1-CRC4 Specific Initialization Table 3-8. E1-CRC4 Specific Initialization. Register Bit Value Comment )05 ;)6 7UDQVPLW &5& PXOWLIUDPH IRUPDW )05 5)6 5HFHLYH &5& PXOWLIUDPH IRUPDW Clock Synchronization Initialization Slave Mode Table 3-9.
The Ethernet Port Initialization Table 3-10. Master Mode Initialization (cont) Register Bit /,0 '&2& 7 Value Comment )RU 7 RQO\ ± 0+] UHIHUHQFH FORFN IRU WKH '&2 5 FLUFXLWU\ SURYLGHG RQ SLQ 6<1& Transmit Pulse Shape For each type of Line Build-Out (LBO), the shape of the transmit pulse must be adjusted through QuadFALC registers LIM0, LIM2, XPM0, XPM1, and XPM2 in order to comply with FCC 68 or ANSI T1.403 (see Table 1-27 on page 31).
Chapter 3: Programming the Peripherals For a simple SMC1 controller example in polling mode: See Boot Firmware: app\c\montty.
The TTY Framer Initialization 86 Interphase Corporation
4Accessing the 4538 on the PCI Side 4 PowerSpan Configuration by the PCI Host Several elements of the PowerSpan are automatically configured at power-up by the hardware, or by the PowerQUICC II. However, some PCI-specific settings have to be done by the PCI host. PCI Configuration The card is identified through its Interphase Vendor ID (0x107E) and its PCI device ID (0x9070).
Controlling the PCI-to-Local Interrupt For a normal use, the card should be reset by the PCI host (if needed) using only the –SRESET signal. The –HRESET signal is used for special cases, such as FLASH memory re-programming through PCI. Example 4-1 is an example of C code routines to reset and run the board from the PCI side. Example 4-1.
Chapter 4: Accessing the 4538 on the PCI Side Local to PCI Interrupt (–INTA) The PowerQUICC II can generate an interrupt toward the PCI Host by setting a doorbell bit. Conventionally, doorbell bit 0 has been dedicated to this task, and has been associated with PCI interrupt pin –INTA in the PowerSpan Interrupt Map registers. Example 4-3 is an example of C code routines to reset the PCI-to-Local interrupt and to read the status of this interrupt from the local side. Example 4-3.
Access to the FLASH EEPROM Through PCI When the processor is running, the PCI bus has access to all the elements connected to the local bus, except the FLASH boot memory: the main SDRAM memory (the processor’s SDRAM memory controller must be initialized), the QuadFALC framers, etc. (the processor must have its chip selects programmed). Local space mapping is the same as when accessed by the processor.
Chapter 4: Accessing the 4538 on the PCI Side ` Example 4-5.
Serial EEPROM Connected to the PowerSpan FLASH EEPROM Programming Algorithms The boot memory is a 4Mx8 AMD 29LV033 FLASH device. To reprogram the AMD FLASH device, special programming algorithms are defined by AMD, which combine reads and writes with special address patterns. The algorithm descriptions can be found at the AMD web site. You can also look or start from the source provided in the BDK (file app\c\amdflash.c).
Chapter 4: Accessing the 4538 on the PCI Side In Situ EPLD Programming Glue logic is implemented in some EPLDs that can be programmed in the field using the PCI interface. The EPLDs are in a daisy-chain configuration, which enables all of them to be programmed at once. They can be programmed in-situ by the PCI host, using PowerSpan interrupts as I/O pins. A jumper must be placed on board location JP1 to enable the programming (when present, this jumper sets the ISP signal –ISPEN to its active state 0).
PCI Deadlock Situations Example: The PCI host sets the DMA buffer descriptors into the local memory, and then it runs the DMA (a write into a PowerSpan register). The DMA starts before the effective completion of the buffer descriptors writes into the local 60x memory, so it loads a bad addresses, a bad byte count, etc., and accomplishes the transfer with this bad data. In this case, the PCI host must ensure that its latest write into the memory is effectively finished locally, before starting the DMA.
5Connectors and Front Panel 5 Connector Placement 3 3RZHU6SDQ &$ / 3 - (WKHUQHW 03& /;7 77< - 6'5$0 3 4XDG)$/& 3(% 6'5$0 - ( 7 - - ( 7 - Figure 5-1. Connectors on the Component Side -3 -3 &38B/(' &38B/(' &38B/(' &38B/(' - '(%8* Figure 5-2.
Front Panel Front Panel - (WKHUQHW /(' /(' /(' /(' /(' /(' - 77< - /LQH - /LQH Figure 5-3.
Chapter 5: Connectors and Front Panel Table 5-1. RJ48 Connectors J1 and J2 Signal ,1 ,1 287 287 Ethernet 10/100 RJ45 Connector J3 Table 5-2.
PMC Connectors TTY Serial Port J4 A 2.5mm stereo jack connector provides a connection to an asynchronous serial device such as a TTY console. Signals on this connector have EIA-232-D electrical levels (RS232) for direct connection to a console. Table 5-3. J4 TTY Serial Connector Pin Signal Ring Ground Tip TxD Sleeve RxD Figure 5-4. TTY connector : 2.
Chapter 5: Connectors and Front Panel Table 5-4. PMC Connector P1 (cont) No. Pin Name Pin Type Description 1RW FRQQHFWHG 1RW FRQQHFWHG *1' 6XSSO\ *URXQG 1RW FRQQHFWHG 3&,B&/.
PMC Connectors Table 5-4. PMC Connector P1 (cont) No.
Chapter 5: Connectors and Front Panel Table 5-5. PMC Connector P2 (cont) No.
PMC Connectors Table 5-5. PMC Connector P2 (cont) No.
Chapter 5: Connectors and Front Panel Table 5-5. PMC Connector P2 (cont) No. Pin Name Pin Type Description 1RW FRQQHFWHG PMC Connector P4 PMC connector P4 supports the four E1/T1 lines and two TDM busses with clocks and synchronization signals. The framers 1, 2, 3 and 4 are respectively tied to the lines 0, 1, 2 and 3. Signal levels are classified in the “Very Low Voltage Directory” by IEC 950 safety standard. Table 5-6. PMC Connector P4 No.
PMC Connectors Table 5-6. PMC Connector P4 (cont) No.
Chapter 5: Connectors and Front Panel Table 5-6. PMC Connector P4 (cont) No.
ISP Enable Jumper JP1 Table 5-7. J5 Debug Port Pin Signal Signal Pin 1 TDO 10 kW Pull-up to +3.3 V 2 3 TDI TRST_N 4 5 QREQ_N +3.3V through a 1 kW resistor 6 7 TCK 8 9 TMS 10 11 SRESET_N 13 HRESET_N 15 10 kW Pull-up to +3.3 V GND 12 14 GND 16 WARNING J5 Debug Connector is not compliant to PMC component height specification. It should be removed to insert the 4538 and its carrier into a CompactPCI chassis.
Chapter 5: Connectors and Front Panel Connector Summary Figure 5-5. 4538 Connectors Connector 3 3 Usage ELW 3&, EXV 3 7HOHFRP &RQQHFWRU - 7 ( - OLQH IURQW SDQHO - 7 ( - OLQH IURQW SDQHO - (WKHUQHW IURQW SDQHO - 56 77< IURQW SDQHO - -7$* GHEXJ SRUW -3 ,63 SURJUDPPLQJ -3 %ODQN FDUG ERRW HQDEOH Carrier Card Specification CompactPCI Carrier Card Interphase has defined a combination of cards to allow 4538 rear access configurations in CompactPCI chassis.
Carrier Card Specification Table 5-8.
Chapter 5: Connectors and Front Panel Signals printed in bold in Table 5-8 and Table 5-9 shall be routed to the corresponding PMC connector (used on 6435 RTM). Signals printed in italics and underlined in Table 5-8 and Table 5-9 shall not be used on the carrier card. They should be routed to the corresponding PMC connector. Signals followed by a (*) sign in Table 5-8 and Table 5-9 may be driven by the carrier card (No connection on the 6435 RTM).
6435 Rear Transition Module 6435 Rear Transition Module 3RZHU Figure 5-6.
Chapter 5: Connectors and Front Panel NOTE PMC site 1 (J14) corresponds to lines 5 to 8, PMC site 2 (J24) corresponds to line 1 to 4 The 6435 RTM is a fully passive module having the same features as the Front Panel T1/E1/J1 (described in Front Panel on page 96). It includes eight T1/E1/J1 line interfaces with all the line safety protections. It does not include any loopback relays or line LEDs. On the rear panel there is one unshielded 8-pin modular jack connector for each T1/E1/J1 line.
6435 Rear Transition Module 112 Interphase Corporation
AMechanical Information A PMC Card Dimensions 'LDPHWHU +ROHV 3/ 5 W\S &/ &/ &/ 'LDPHWHU +ROH IRU 9 .H\ &/ 'LDPHWHU +ROH IRU 9 .H\ &/ .HHS RXW , 2 DUHD .
Carrier Card Dimension Requirements Carrier Card Dimension Requirements )URQW 3DQHO 2SHQLQJ [ &KDPIHU DOO DURXQG PP GLDPHWHU FRPSRQHQW .HHSRXW DUHD DURXQG VWDQGRIIV DQG .H\ SRVLWLRQV 'LDPHWHU +ROHV 3/ .H\ 3RVLWLRQ IRU 9 &/ &/ &/ .H\ 3RVLWLRQ IRU 9 &/ 5HVWULFWHG &RPSRQHQW $UHD &/ .
Bibliography Industry Standards EIA-232-D: Interface Between Data Terminal Equipment and Data Circuit-Terminating Equipment Employing Serial Binary Data Interchange (OHFWURQLF ,QGXVWULHV $OOLDQFH :LOVRQ %RXOHYDUG $UOLQJWRQ 9$ 7HOHSKRQH :HE KWWS ZZZ HLD RUJ ECTF H.110 Hardware Compatibility Specification: CT Bus, Revision 1.
PICMG 2.0 CompactPCI Specification PICMG 2.5 CompactPCI Computer Telephony Specification PICMG 2.
ANSI T1.107-1995: Digital Hierarchy - Formats Specifications. ANSI T1.646-1995: Broadband ISDN - Physical Layer Specification for User-Network Interfaces Including DS1/ATM. $PHULFDQ 1DWLRQDO 6WDQGDUG IRU 7HOHFRPPXQLFDWLRQV $16, $PHULFDQ 1DWLRQDO 6WDQGDUG ,QVWLWXWH :HVW QG 6WUHHW 1HZ
1 specification and test principles. ETSI ETS 300 166 - Transmission and Multiplexing (TM); Physical and electrical characteristics of hierarchical digital interfaces for equipment using the 2 048 kbit/s - based plesiochronous or synchronous digital hierarchies. ETSI ETS 300 233 - Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate. (XURSHDQ 7HOHFRPPXQLFDWLRQV 6WDQGDUGV ,QVWLWXWH (76, 6RSKLD $QWLSROLV KWWS ZZZ HWVL RUJ ITU-T G.
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120 Interphase Corporation
Glossary AAL u ATM Adaptation Layer Service-dependent sublayer of the data link layer. The AAL accepts data from different applications and presents it to the ATM layer in the form of 48-byte ATM payload segments. AALs consist of two sublayers: CS and SAR. AALs differ on the basis of the source-destination timing used, whether they use CBR or VBR, and whether they are used for connection-oriented or connectionless mode data transfer.
Glossary u Basic Rate Interface ISDN interface composed of two B Channels and one D Channel for circuitswitched communication of voice, video, and data. BSP u Board Support Package A board support package consists of documentation and software used to configure and install a specific operating system on a specific product.
Glossary DSX1 DTE u Cross-connection point for DS1 signals. u Data Terminal Equipment Device at the user end of a user-network interface that serves as a data source, destination, or both. DTE connects to a data network through a DCE device (for example, a modem) and typically uses clocking signals generated by the DCE. DTE includes such devices as computers, protocol translators, and multiplexers. E1 u Wide-area digital transmission scheme used predominantly in Europe that carries data at a rate of 2.
Glossary ITU-T u International Telecommunication Union Telecommunication Standardization Sector International body that develops worldwide standards for telecommunications technologies. The ITU-T carries out the functions of the former CCITT. J1 u Japanese transmission standard LAN u Local-Area Network High-speed, low-error data network covering a relatively small geographic area (up to a few thousand meters).
Glossary u Protocol Data Unit A message of a given protocol comprising payload and protocol-specific control information, typically contained in a header. PLP u Packet Level Protocol Network layer protocol in the X.25 protocol stack. Sometimes called X.25 Level 3 and X.25 Protocol. PMC u PCI Mezzanine Card PCI “daughter” card designed to mount on a “mother card”. PDU POST card.
Glossary u Synchronous Transport Signal STS1 u Synchronous Transport Signal level 1 Basic building block signal of SONET, operating at 51.84 STS Mbps. Faster SONET rates are defined as STS-n, where n is a multiple of 51.84 Mbps. SVC u Switched Virtual Circuit Virtual circuit that is dynamically established on demand and is torn down when transmission is complete. SVCs are used in situations where data transmission is sporadic. Called a switched virtual connection in ATM terminology.
Index When using this index, keep in mind that a page number indicates only where referenced material begins. It may extend to the page or pages following the page referenced. B T BIST Built-in Self Test ........................................ 14 T1 Transmit Pulse Shape programming ................ 75 Transmit Pulse Shape programming ..................... 31 types .................................................................. xii C Cache Line Size ..................................................
