V/Ethernet 4221 Condor User’s Guide Document No.
Copyright Notice Copyright 1993, 1994 by Interphase Corporation All rights reserved No part of this publication may be stored in a retrieval system, transmitted, or reproduced in any way, including, but not limited to photocopy, photograph, electronic, or mechanical, without prior written permission of: Interphase Corporation 13800 Senlac Dallas, Texas 75234 Phone: (214) 919-9000 FAX: (214) 919-9200 Disclaimer Information in this user document supercedes any preliminary specification, data sheets, and/or
For Assistance To place an order for an Interphase product, call: Sales Support: (214) 919-9000 For assistance using this, or any other Interphase product, call: Customer Service: (214) 919-9000 United Kingdom: +44-869-321222 To send in a board for repair or upgrade, call: RMA Coordinator: (214) 919-9000 Trademark Acknowledgments All terms used in this manual that are known to be trademarks or service marks are listed below.
TABLE OF CONTENTS CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scope Of Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Response Block (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Command Response Status Word (CRSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Command Tag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 IOPB Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAC status/control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel 82596 Status/Control – Transmit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel 82596 Status/Control – Receive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAC returned information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LIST OF FIGURES Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. 4221 Condor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 10BaseT Condor Motherboard Layout (PB04221-000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Single Channel AUI or 10BaseT Motherboard Layout (PB004221-001) . . . . . . . . . . . . . . . 10 AUI Condor Motherboard Layout (PB04221-000) . . . . .
xiii
LIST OF TABLES Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 2-16. Table 2-17. Table 2-18. Table 2-19. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21. Table 3-22. Table 3-23. Table 3-24. Table 3-25. Table 3-26.
Table 3-36. Table 3-37. Table 3-38. Table C-39. Table C-40. Table C-41. Table C-42. Table C-43. Table C-44. Report Network Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Command Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Network Statistics Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 1 INTRODUCTION Intended Audience Interphase wrote this manual for its customers. It is intended for a highly technical audience, specifically, users who need to write their own software drivers. Readers are assumed to have extensive knowledge of the following: • The C programming language, including experience writing and installing interface software (drivers). • The operating system of the host computer. • Ethernet specifications. • VME specifications.
Chapter 1 - Introduction Conventions This section details many of the writing conventions used throughout the manual. In addition, it gives many of the technical conventions. • The V/Ethernet 4221 Condor will be referred to by the name Condor or referenced as the controller. • Byte represents 8 bits; word represents 16 bits (2 bytes); and longword represents 32 bits (2 words, 4 bytes). • Binary (single bit) data is represented as either 1 or 0.
Options Options Interphase Corporation offers the following Condor options: • Dual Channel Ethernet (AUI) • Dual Channel Ethernet (10BaseT) • 3 Channel Ethernet (AUI or 10BaseT) • Quad Ethernet Channel (AUI or 10BaseT) Physical Description The Condor physically conforms to the 6U VMEbus board standard. The board requires the VMEbus +5 (+/- 5%) volt supply. The board supports two channels on the main board with the associated channel connectors and up to two channels on daughter card.
Chapter 1 - Introduction Ethernet Front End Channel (FEC) The 82596CA® Local Area Network (LAN) Co-processor is used as the FEC Ethernet controller. The 82596CA® communicates with the rest of the board through the LBUS. The 82596CA® has a 80486® type bus interface, which requires two PALs to convert the 80486® interface to meet the LBUS (MC68040_ type) specification. The 82596CA® can be a master or a slave of the LBUS.
VMEbus Short I/O Interface VMEbus Short I/O Interface The VMEbus Short I/O interface allows for VMEbus host and onboard CPU communications. The host issues commands to the Condor through the Short I/O interface and the CPU issues status back to the host. The Short I/O Interface is a Slave-only interface to the Condor and contains two independent, jumper-configurable, slave-access areas. The areas can be configured to be 256, 512-, 1K- or 2K- bytes in length.
Chapter 1 - Introduction interrupt handler outputs an interrupt vector number for the non-DMA engine interrupts or requests access to the LBUS for a DMA engine IACK cycles. CPU/LBUS Interface The CPU/LBUS Interface links the CPU core with the LBUS resources. The CPU/LBUS interface converts the CPU Core bus to the LBUS. The Interface is a one-way interface which allows the CPU to act as a LBUS master. The interface does not allow other LBUS masters to access the CPU Core.
CHAPTER 2 HARDWARE INSTALLATION Overview Before attempting installation, read this chapter thoroughly to insure the safe installation of the Condor into your system. If you have any questions regarding installation, which are not answered in this chapter, please contact Interphase Customer Service at (214) 919-9111.
Chapter 2 - Hardware Installation The daughter card installation procedure will vary depending on the desired configuration. Variables include: • Single Channel AUI/10BaseT. • Dual Ethernet AUI. • Dual Ethernet 10BaseT. The following table summarizes the Condor products that are available from Interphase to implement various combinations of the above functions. Table 2-1.
Overview J13 LED 6 J12 F E C 0 J10 J11 J9 LED 7 F E C 1 P1 J4 J3 SPA J8 LED 5 J22 J21 J20 J26 J25 J24 J19 J23 J7 J6 J5 LED 4 LED 3 LED 2 J2 LED 1 SPB J1 J16 J17 J18 J15 J14 OPTIONAL DAUGHTER CARD P2 Figure 2-1.
Chapter 2 - Hardware Installation J13 LED 6 J12 F E C 0 F E C 0 J11 10BaseT J9 AUI P1 J4 J3 SPA J8 LED 5 J7 J6 J5 LED 4 J14 J15 J16 J J 1 1 7 8 J22 J21 J20 J26 J25 J24 J19 J23 LED 3 LED 2 J2 LED 1 SPB J1 P2 Figure 2-2.
Overview J13 F E C 0 J12 J10 J11 F1 J9 F E C 1 P1 J4 J3 SPA J8 LED 6 J7 J6 J5 LED 5 LED 4 LED 3 J22 J21 J20 J26 J25 J24 J19 J23 J2 LED 2 LED 1 J1 SPB J16 J17 J18 J15 J14 OPTIONAL DAUGHTER CARD P2 Figure 2-3.
Chapter 2 - Hardware Installation J15 LED 6 J12 F E C 0 J11 LED 7 F E C 1 J9 P1 J4 J3 SPA J8 LED 5 J7 J6 J5 LED 4 J10 J14 J16 J J 1 1 7 8 J22 J21 J20 J26 J25 J24 J19 J23 LED 3 LED 2 J2 LED 1 SPB J1 OPTIONAL DAUGHTER CARD P2 Figure 2-4.
Overview J15 F E C 0 J12 J11 F1 J9 F E C 1 P1 J4 SPA J3 J8 LED 6 J7 J6 J5 LED 5 LED 4 LED 3 J10 J2 J14 J16 J J 1 1 7 8 J22 J21 J20 J26 J25 J24 J19 J23 LED 2 LED 1 J1 SPB OPTIONAL DAUGHTER CARD P2 Figure 2-5.
Chapter 2 - Hardware Installation 4221 Condor Hardware Installation Procedures For proper installation of the Condor, it is imperative that you use the following procedures. Step 1. Visual Inspection Before attempting the installation of this board, make sure you are wearing an anti-static or grounding device. Remove the Condor board from the anti-static bag, and visually inspect it to ensure no damage has occurred during shipment.
4221 Condor Hardware Installation Procedures Board Status LEDs LEDs 1, 2, 3, and 4 are Board Status LEDs which provide the following functions: • Power On Self Test (POST) Mode • Monitor Mode • Run Mode POST Mode: This mode provides diagnostics for the CPU and Buffer. Refer to the following table for a list of diagnostics performed while in this mode: Table 2-3.
Chapter 2 - Hardware Installation Table 2-4. Run Mode LED Matrix LED1 LED2 LED3 LED4 Function ON OFF OFF OFF 1-4 Commands On Board ON ON OFF OFF 5-16 Commands On Board ON ON ON OFF 17-64 Commands On Board ON ON ON ON 65 or More Commands On Board Step 3. Set Onboard Motherboard Jumpers Set all onboard jumpers so that the Condor is properly configured for operation within your system. The board layout as illustrated in figure 2-1 shows the location of the jumpers.
4221 Condor Hardware Installation Procedures J9 +12 VOLTS Flash Programming Protect: J9 J9 (PB04221-000) (PB04221-001) IN: +12 Volt power connected to EPROM socket. OUT: +12 Volt power disconnected from EPROM socket. J12 VME Bus Grant: 2 16 J12 15 1 Pins 1 - 12 Reserved Pins 13 - 16 VME Bus Grant: Table 2-5.
Chapter 2 - Hardware Installation (Pins 5-6) Console Message Disable IN = Disable OUT = Enable (Pins 7-8) GDB Enable Point IN = GDB Initialized On Exit OUT = GDB Initialized On Reset J14 Firmware Option Jumpers: 8 7 2 8 1 7 J14 2 J14 1 (PB04221-001) (PB04221-000) (Pins 1-2) 16 Bit Block Enable (default = OUT) IN = 16 bit Block Mode Disabled OUT = 16 bit Block Mode Enabled (Pins 3-4) Sysfail (default = OUT) IN = Clear Sysfail after passing diagnostics OUT = Clear Sysfail before running Powe
4221 Condor Hardware Installation Procedures Table 2-6. Secondary Short I/O J15 PINS 5-6 OUT OUT IN *IN SIZE (Bytes) 7-8 OUT IN OUT *IN 256 bytes of Secondary Short I/O space 512 bytes of Secondary Short I/O space 1K bytes of Secondary Short I/O space 2K bytes of Secondary Short I/O space* * Factory Default J16 Primary Short I/O Size / Reset Enable: Table 2-7.
Chapter 2 - Hardware Installation J18 Primary Channel Address Modifiers: J18 IN = Primary Channel Address Modifiers 29 or 2D OUT = Primary Channel Address Modifier 2D only 20
4221 Condor Hardware Installation Procedures J19, J20, J21 & J22 Primary Short I/O Base Address: J22 J21 J20 1 2 J19 15 16 Refer to the following tables when setting Primary Short I/O Base Addresses for the following: • Primary Short I/O For 2K Base Address • Primary Short I/O For 1K Base Address • Primary Short I/O For 512 Bytes Base Address • Primary Short I/O For 256 Bytes Base Address NOTE: The normal 4221 configuration is with the Primary Short I/O space disabled.
Chapter 2 - Hardware Installation Table 2-8.
4221 Condor Hardware Installation Procedures Table 2-9.
Chapter 2 - Hardware Installation Table 2-10.
4221 Condor Hardware Installation Procedures Table 2-10.
Chapter 2 - Hardware Installation Table 2-11.
4221 Condor Hardware Installation Procedures Table 2-11.
Chapter 2 - Hardware Installation Table 2-11.
4221 Condor Hardware Installation Procedures Table 2-11.
Chapter 2 - Hardware Installation Table 2-11.
4221 Condor Hardware Installation Procedures Table 2-11.
Chapter 2 - Hardware Installation Table 2-11.
4221 Condor Hardware Installation Procedures J23, J24, J25 & J26 Secondary Short I/O Address: J26 J25 J24 1 2 J23 15 16 Refer to the following tables when setting Secondary Short I/O Base Addresses for the following: • Secondary Short I/O For 2K Base Address • Secondary Short I/O For 1K Base Address • Secondary Short I/O For 512 Bytes Base Address • Secondary Short I/O For 256 Bytes Base Address NOTE: The short I/O interface of the 4221 Condor is accessed through the Secondary Short I/O space
Chapter 2 - Hardware Installation Table 2-12.
4221 Condor Hardware Installation Procedures Table 2-13.
Chapter 2 - Hardware Installation Table 2-13.
4221 Condor Hardware Installation Procedures Table 2-14.
Chapter 2 - Hardware Installation Table 2-14.
4221 Condor Hardware Installation Procedures Table 2-14.
Chapter 2 - Hardware Installation Table 2-14.
4221 Condor Hardware Installation Procedures Table 2-15.
Chapter 2 - Hardware Installation Table 2-15.
4221 Condor Hardware Installation Procedures Table 2-15.
Chapter 2 - Hardware Installation Table 2-15.
4221 Condor Hardware Installation Procedures Table 2-15.
Chapter 2 - Hardware Installation Table 2-15.
4221 Condor Hardware Installation Procedures Step 4.
Chapter 2 - Hardware Installation Ethernet Single Channel AUI/10BaseT Daughter Card COMPONENT SIDE P4 P6 D B 1 5 F1 P5 LED 1 R J 4 5 Figure 2-6. Ethernet Single Channel AUI/10BaseT Daughter Card NOTE: LED3 is located on the solder side of the daughter card and is not shown in this illustration. The Ethernet Single Channel AUI/10BaseT Daughter Card provides two types of connectors (DB15 & RJ45) as shown in Figure 2-7 above. However, only one connection (either AUI or 10BaseT) can be used at a time.
4221 Condor Hardware Installation Procedures Dual Channel 10BaseT Ethernet Daughter Card COMPONENT SIDE P6 LED 2 P4 R J 4 5 P5 LED 1 R J 4 5 Figure 2-7. Dual Channel 10BaseT Ethernet Daughter Card The Dual Channel 10BaseT Ethernet Daughter Card provides two RJ45 connectors as shown in Figure 2-7 above. Table 2-17.
Chapter 2 - Hardware Installation Ethernet Dual Channel AUI Daughter Card COMPONENT SIDE P4 P6 D B 1 5 F1 P5 P3 D B 1 5 Figure 2-8. Ethernet Dual Channel AUI Daughter Card NOTE: LED3 is located on the solder side of the daughter card and is not shown in this illustration. The Dual Channel AUI Ethernet Daughter Card provides two DB15 connectors as shown in Figure 2-8 above. Table 2-18.
4221 Condor Hardware Installation Procedures Step 5. Power Off System Once the board is configured, ensure that the host system and peripherals are turned OFF. CAUTION System power and peripheral power must be turned OFF before attempting to install the Condor. Failure to do so may result in severe damage to the board and/or system. Step 6. Cabling Procedure The cabling procedure depends on how you wish to configure the system. Your options are summarized in Table 2-19. Table 2-19.
Chapter 2 - Hardware Installation RS232 Connectors And Cables There are two 10 pin connectors (2x5 Headers) which are used as the RS232 port cable connectors. These connectors are the same type used for the second serial port I/O Extension-X.2 of PC compatible machines. The connectors are labeled "SPA" and "SPB" (refer to Figure 2-1 or Figure 2-3 for location) for Serial Port A and Serial Port B respectively. Both RS232 ports on the Condor are configured as Data Terminal Equipment (DTE).
CHAPTER 3 MACSI HOST INTERFACE Introduction This chapter defines the MACSI host interface for the Interphase V/Ethernet 4221 Condor. The Condor and its MACSI host interface are designed to be backwards compatible with the Interphase V/Ethernet 4207 Eagle MACSI host interface.
Chapter 3 - MACSI Host Interface Field Offset The value in the far left column specifies the field offset. This value measures increments of 16 bits from the beginning of the record, and may be thought of as the displacement to be added to a pointer to short integer data type required to differentiate the particular field.
System Interface System Interface This section defines how the host communicates with the controller. The shared memory interface is defined, and each major section described in detail. Full definitions for particular commands (what is communicated) can be found in a following section. MACSI Organization Ethernet MACSI for the Condor consists of eight major sections, as illustrated in the following memory map: Table 3-1.
Chapter 3 - MACSI Host Interface The Master Command Entry (MCE) and Command Queue Entries (CQE) are used to queue commands from the host to the controller. A Command Queue Entry (in either the CQE or MCE) is a 12-byte block containing all of the information needed for the 4221 to locate and execute a command issued by the host. Control commands, such as Initialize Controller, are submitted through the MCE. Transmit and Receive commands are submitted through the CQE.
Master Control Status Block (MCSB) Master Control Status Block (MCSB) The MCSB consists of a Master Status Register, which is used to report information from the controller to the host, and the Master Control Register, which provides infrequently used control functions to the host. Table 3-2.
Chapter 3 - MACSI Host Interface Master Control Register (MCR) The MCR provides the host with infrequently used services. These bits are both set and cleared by the host. The controller clears these bits on power up, and does not alter them at any other time. Table 3-4. Master Control Register Master Control Register Addr 15 14 0x004 13 12 11 10 9 8 SFEN RST 7 6 5 4 3 2 1 0 SQM Start queue mode (SQM) This bit is provided for compatibility with the 4207 Eagle MACSI interface.
Onboard Command Queue Entry Onboard Command Queue Entry The host issues a command to the controller through a Command Queue Entry (CQE). Two types are provided: the Master Command Entry (MCE), located at offset 0x0010 is used to issue control commands, such as Initialize Controller, Report Network Statistics, and the like. The normal Command Queue Entry (CQE) is a circular queue of CQE elements located immediately after the MCE, which the host uses to post Transmit and Receive commands.
Chapter 3 - MACSI Host Interface Fetch offboard (FOB) Setting this bit makes the Command Queue entry an offboard entry. Please see the following section for details. Fetch offboard in progress (FIP) This bit is used internally by the controller. It’s value should not be used by the host driver. IOPB Address This field contains a pointer to the IOPB for the command being issued, and is specified as an offset, in bytes, from the start of Short I/O space.
Offboard Command Queue Entry DMA Transfer Control Word This field specifies how the controller should DMA transfer the data from host memory. This field is fully defined in the Common IOPB Structure definition, in the following section. Please refer there for full details. Host Address This field contains the physical address of the command, arranged in a big-endian order.
Chapter 3 - MACSI Host Interface Command Response Block (CRB) The CRB is used by the controller to post completed commands back to the host. It consists of the following fields: Table 3-8.
Command Response Block (CRB) Error (ER) This bit is set with Command Complete when a returned IOPB completed with an error. Errored commands are never returned via the Multiple Completion mechanism. The nature of the error can be determined by examining the Return Status field in the returned IOPB. Exception (EX) This bit is set with Command Complete to indicate that the command completed with some kind of exception, which can be determined by examining the Return Status field in the returned IOPB.
Chapter 3 - MACSI Host Interface Multiple Completed Returned IOPB Structure When multiple commands are returned from the controller to the host with a single interrupt, the following structure is used to return individual commands, starting in the location of Short I/O normally used for the returned IOPB, and continuing for a maximum of 24 entries. Table 3-10.
Configuration Status Block (CSB) Configuration Status Block (CSB) The controller uses the CSB to report the firmware and hardware configuration upon power up. These contents are valid from the time Board OK is asserted, to the time the controller posts back multiple completed returned commands in this space. The following fields are defined: Table 3-11.
Chapter 3 - MACSI Host Interface Firmware Revision Level The firmware revision level, represented as a 3-digit ASCII value. Firmware Revision Date The revision date of the installed firmware, represented as 8 ASCII digits. For example, a release data of January 15, 1994 would be represented as 01151994. Ethernet MAC Addresses (Ports 0 - 3) These field contain the current physical node addresses used to filter incoming receive packets for up to 4 Ethernet ports.
Controller Statistics Block Controller Statistics Block This space was used to report network statistics in the original Eagle MACSI implementation for single port Ethernet support. Statistics for multi-port controllers, or single port implementations not requiring Eagle MACSI compatibility, should be obtained via the Report Network Statistics IOPB. The contents of this area are undefined for multi-port controllers, and are overwritten in any case with multiple completed commands.
Chapter 3 - MACSI Host Interface Controller Statistics Block Addr 15 14 13 12 11 10 9 8 7 0x7CC to 0x7CF Receive 82596 Completions 0x7D0 to 0x7D3 Successful Receives 0x7D4 to 0x7D7 Failed Receives 0x7D8 to 0x7DB Receive DMA Completions 0x7DC to 0x7DF 6 Receive Completions Posted to Host 0x7E0 to 0x7FC Reserved Transmit Commands Submitted Total number of attempted frame transmissions (successful and unsuccessful).
Controller Statistics Block Transmit Completions Posted to Host Total number of frame completions posted to the Command Response Block and Returned IOPB. Receive Commands Submitted Total number of attempted message receptions (successful and unsuccessful). Receives Dropped - No Pending Receive Command Number of frame receptions lost or ignored because the host had no outstanding Receive commands posted to the Condor.
Chapter 3 - MACSI Host Interface IO Parameter Blocks (IOPBs) This section provides a detailed description of each of the commands used by the host to communicate with the controller. Each command is listed below, along with the code associated with each command. Table 3-13.
Common IOPB Structures Command Code This field specifies the command to be executed. Particular values are noted for each of the individual commands. Command Options This field specifies operational parameters or options to be associated with the execution of the command. The following subfields are available for all commands: Table 3-15.
Chapter 3 - MACSI Host Interface Address modifier This field contains the VMEbus address modifier used for the transfer. Refer to your system documentation for possible values for this field. Memory type (MT) This 2-bit field specifies the width of the data transfers. Permitted values are: Table 3-17.
Initialize Controller Initialize Controller This command allows the host to specify global configuration parameters, and initializes the controller for use within a particular system. Configurable parameters include the number of CQE entries, global DMA control parameters, and possible offboard locations for posting back returned commands. In addition, this command can be used to associate station addresses with each of the attached ports.
Chapter 3 - MACSI Host Interface Controller Initialization Block (CIB) The CIB contains the actual values to use when initializing the controller. It may be located anywhere in Short I/O, though it makes sense to place it after the MCE and before the Command Response Block. Table 3-20.
Controller Initialization Block (CIB) Special Network Options Originally, this field allowed the host to set several network related options, such as disabling receives, or disabling transmit CRC. A multiport controller requires that this type of control be associated with a particular port, rather than as a global configuration parameter, so these types of functions have been moved to the MAC Control IOPB.
Chapter 3 - MACSI Host Interface A value between 1 and 0x20 (40 decimal) causes the controller, after being granted the bus, to transfer data until 1) there is no more data, or 2) 16 micro seconds elapses, or 3) one of the bus request lines on the VMEbus is asserted. With a value between 0x21 and 0x80, the controller, after being granted the bus, will transfer data until 1) there is no more data to be transferred, or 2) 32 microseconds elapses.
MAC Control/Status MAC Control/Status This command provides a host driver with two distinct levels of service to an Ethernet port located on the 4221. First, it provides a general mechanism to control the Ethernet port, without the driver having to know any particulars about the actual Ethernet interface chip being used. Drivers written for long-term portability should use these features.
Chapter 3 - MACSI Host Interface Table 3-22.
MAC Control/Status Command Options Table 3-23. Command Options Command Options Offst 15 14 13 12 11 0x01 10 AR 9 8 AN AA 7 6 5 Port 4 3 2 1 SRX STX SM 0 IE Interrupt Enable (IE) Defined in Common IOPB Structures. Set MAC options (SM) When this bit is set, the state of the specified MAC is updated as per those bit settings specified in the MAC Status/Control word.
Chapter 3 - MACSI Host Interface Abort Report (AR) Setting this bit causes commands aborted with either the AA or the AN bit to be reported back to the host with the appropriate error code set. Setting this bit has no effect on pending receives for particular ports aborted via the Abort Pending bit in the MAC Status/Control field.
MAC Control/Status Setting this bit resets the port: promiscuous mode is disabled, multicast is disabled, any supplied multiple individual addresses are lost. All of the internal memory structures for the port are reinitialized, and the port is reinitialized with power on default values. Enable/Disable MAC (EM) With SM set, setting this bit enables the MAC for both transmits and receives. If this bit is not set, the port will not transmit, nor will it receive. Without SM, the bit reports status.
Chapter 3 - MACSI Host Interface Table 3-25. Intel 82596 Transmit Status / Control Intel 82596 Transmit Status/Control Offst 15 14 0x0C 0x0D 13 12 11 10 9 8 Interframe Spacing Max Entry 7 6 5 EXP PRI AR 4 3 LIN PRI 2 1 0 DB BM Slot Time Backoff method (BM) (p. 4-131) This parameter determines when to start the back-off timeout. Disable backoff (DB) (p. 4-141) Disables the backoff algorithm implemented in the 82596. Linear priority (LIN PRI) (p.
MAC Control/Status Table 3-26. Intel 82596 Receive Status / Control Intel 82596 Receive Status/Control Offst 0x0E 0x0F 15 14 LPBK DG 13 12 11 MONM 10 9 8 7 6 5 ADDR LEN DU TDR 4 3 MI MS 2 1 MA BD 0 SB Min Frame Length Save bad frames (SB) (p. 4-129) When set bad frames (CRC error, Alignment error, etc.) are sent to the host. Broadcast disable (BD) (p. 4-134) Disables reception of frames with a Broadcast destination address or Multicast of all 1’s. Multicast all (MA) (p.
Chapter 3 - MACSI Host Interface Time domain reflectometry test (TDR) (p. 4-150) This operation activates the Time Domain Reflectometry test. The result is returned in the MAC returned information field. Refer to the 82596 documentation for full details of the returned values. Dump 89596 internal registers (DU) (p. 4-153) This command will cause the contents of the various 82596 registered to be transferred to the location in system memory specified by the Buffer Address field. Diagnose (DG) (p.
Change Default Node Address Change Default Node Address This command is used to change the 48 bit physical address associated with any of the attached ports. It also can be used to manage both the factory and user addresses stored in NVRAM, either by setting them to new values, or by restoring preset values. This command must be issued through the Master Command Entry. Table 3-27.
Chapter 3 - MACSI Host Interface Command Options Table 3-28. Command Options Command Options Offst 0x01 15 14 13 12 PFM 11 10 9 8 RUD RFD 7 6 5 4 Port 3 2 1 0 RMC UUD IE Interrupt enable (IE) As defined in the Common IOPB Structures. Update user default (UUD) Setting this bit updates the NVRAM-stored user default physical node address for the specified port with the value provided in the Physical Node Address field.
Transmit Transmit The Transmit command causes the controller to DMA transfer the specified frame from host memory, and then transmit it (if possible) through the specified Ethernet port. Table 3-29.
Chapter 3 - MACSI Host Interface Command Options Table 3-30. Command Options Command Options Offst 15 14 13 12 11 10 0x01 9 8 RSV 7 DMC 6 5 Port 4 3 IG 2 1 0 RSV RSV IE Interrupt enable (IE) As defined in Common IOPB Structures. In-line gather (IG) Setting this bit allows the host to define the frame location in system memory as a set of address/count pairs. These gather elements are specified directly in the remainder of the IOPB, and do not require a separate DMA of a gather-list.
Transmit -- In-Line Gathers Table 3-31. Transmit - In-Line Gathers Transmit - In-Line Gathers Offst 15 14 13 12 11 10 9 8 7 6 0x06 Number of Elements 0x07 Total Transfer Count 0x08 Reserved 0x09 Element Transfer Count 0x0A Buffer Address (MSW) 0x0B Buffer Address (LSW) 0x0C Reserved 0x0D Buffer Address (MSW) 0x0F Buffer Address (LSW) 5 4 3 2 1 0 ... Number of Elements This field contains the number of gather elements included in the IOPB.
Chapter 3 - MACSI Host Interface Receive The host provides the controller with Receive commands, which specify the host resources to be used for incoming frames. As frames come in, the controller transfers them to the specified host memory locations, updates the provided Receive commands, and posts them back to the host. Receive commands may be allocated to particular ports, or they may be placed in a "free pool", and the controller will use them as needed.
Receive Command Code This field must contain 0x60 to execute the Receive IOPB. Command Options Table 3-33. Command Options Command Options Offst 0x01 15 14 13 12 11 10 9 8 AN Y 7 DMC 6 5 4 PORT 3 2 1 0 RSV RSV IE Interrupt enable As defined in the Common IOPB Structures section. Port selector This field specifies the port to which the receive resources will be allocated. Valid ports range from 0 to 3.
Chapter 3 - MACSI Host Interface Source Address When so monitoring the network, the source address for the incoming frame will be contained in this field. Neither this field nor the previous will be used for normal frame reception activity.
Initialize Multiple Completions Initialize Multiple Completions This command enables the controller to return multiple completed commands to the host with a single completion via the Command Response Block, with a single (optional) interrupt. When commands are completed using this mechanism, the returned IOPB is replaced with a substantially different Multiple Completion Returned Command structure. Please refer to the system interface section of this chapter for details.
Chapter 3 - MACSI Host Interface Command Options No special options are available for this command. Refer to Common IOPB structures for defined options. Return Status There are not particular errors currently defined for this IOPB. Control Flags Table 3-35. Control Flags Control Flags Offst 15 14 13 12 11 10 9 8 0x06 7 6 5 4 3 2 1 0 MIE MEN Enable Multiple Completions (MEN) Setting this bit enables posting of multiple commands completions.
Report Network Statistics Report Network Statistics Table 3-36.
Chapter 3 - MACSI Host Interface Command Options Table 3-37. Command Options Command Options Offst 15 14 13 12 11 10 9 8 0x01 7 6 5 4 3 2 1 Port 0 IE Interrupt enable (IE) As defined in Common IOPB Structures. Port selector This field specifies the port for which the statistics will be reported. Valid ports range from 0 to 3. Return Status This field will contain any return status from the controller to the host.
Network Statistics Block Network Statistics Block Table 3-38.
Chapter 3 - MACSI Host Interface Transmits Failed This field contains the number of transmit commands for the particular port that could not be transmitted out over the media, due to excessive collisions. Collisions This field contains the total number of collisions for the particular interface. Receives Submitted This field contains the number of receive commands submitted to the controller by the host for the particular port.
APPENDIX A SPECIFICATIONS VMEbus Specifications DTB Master DTB Slave Requester Interrupter A16, A24, A32, D08 (EO), D16, D32: BLT, D64: BLT A16, D08 (EO), D16, D32 Any of R(0-3), Static RWD, ROR Any of I(1-7), Dynamic D08 (O) Power Requirements Dual AUI Ethernet Motherboard 5.70A typical @ +5V DC (+/- 5%) 6.20A maximum @ +5V DC (+/- 5%) 7mA maximum @ +12V DC (+/- 5%) See note. 30mA maximum @ -12V DC (+/- 5%) Dual 10BaseT Ethernet Motherboard 5.70A typical @ +5V DC (+/- 5%) 6.
Appendix A Mechanical (Nominal) Length Width Thickness Weight 233 mm 160 mm 20 mm .45 Kg Operating Environment Temperature Relative Humidity Air Flow 0-55 degrees Centigrade 10% - 90% Noncondensing 250 CFM Minimum Fuse The AUI version of the Condor has a 1.5 amp fuse (F1) used to protect the +12 volts power when provided by the Condor. LITTLEFUSE part number is PN 273-01.5. To determine the location of the fuse on the board, refer to the appropriate board layout.
APPENDIX B CONNECTOR PINOUTS AND CABLING Overview This chapter contains the connector pinouts and cabling information needed for various Condor configurations. The tables in this chapter are listed below.
Appendix B VMEbus Connectors The following tables show the pin numbers and signal description for the P1 and P2 VMEbus Connectors. • Table C-39 - P1 Connector Signal Descriptions (All Versions) • Table C-40 - P2 Connector For Motherboards Which Only Uses P2 Row B P1 Connector Table C-39.
VMEbus Connectors P2 Connector Row B Only Version Table C-40.
Appendix B Ethernet Connectors and Pinouts The Condor supports both the AUI and 10BaseT versions of the Ethernet 802.3 specification. The card will have a 15 pin "D" connector used for the AUI signals and a RJ45 connector for unshielded twisted pair (10BaseT). Transformers are used with both interfaces to isolate the external cable from the interface electronics. The single-channel daughter card is manufactured with both of connectors.
Ethernet Connectors and Pinouts AUI Connector Signals The AUI signals and connector pinout for the DB15 connector are shown in the following table. Table C-42.
Appendix B RS232 Connector and Cable Table C-43.
APPENDIX C ERROR CODES The Return Status word in the command response contains information pertaining to the status of the IOPBs returned in the Command Response Block. Error codes are reported in hexadecimal format. HEX CODE DESCRIPTION 0x110 VMEbus Error An attempted VME bus transfer generated a system bus error. 0x115 Abort Pending Error The errored command is being returned in response to an abort command issued by the MAC Status IOPB.
Appendix B 108
INDEX Controller Initialization Block (CIB) 74 Controller Initialization Block Offset 73 Controller Panic 63 controller reset (RES) 58 Controller Reset (RST) 58 Controller Statistics Block 56 CPU core 5, 6 CQE 56, 59, 74, 88 CRB 56, 62, 76 CRBV 62, 76 CRSW 62 CSB 65 customer service 7 Numerics 82596 4, 81, 82 A AA 79 Abort ALL (AA) 79 Abort ANY (AN) 79 Abort Pending (AP) 81 Abort Report (AR) 80, 81 Air Flow 100 AN 79 ANY 91 AP 81 AR 80, 81 D Data Valid Indicator 97 daughter card dual 10BaseT 8, 49, 99 du
EX 63 Exception (EX) 63 secondary short I/O size 18 VME bus grant 17 F L feature list 2 fetch offboard entry (FOB) 60 Fetch offboard in progress (FIP) 60 field offset 54 FIP 60 firmware revision level 66 FOB 60 Front End Channel (FEC) 3, 4 fuse 14, 100 G LEDs board status 15 diagnostic 14 dual 10BaseT daughter card 49 dual AUI daughter card 50 run mode 16 single channel AUI/10BaseT daughter card 48 Local Bus (LBUS) 4 longword 2 loopback (LPB) 81 LPB 81 go bit 59 grounding 14 M MAC Control/Status 77,
STX 79 P PFM 86 PM 75, 81 POST mode 15 power requirements 99 Product Code 65, 68 Program factory MAC address (PFM) 86 Promiscuous mode (PM) 75, 81 T TDR 81 TDR test 81 Temperature 100 Transfer Count 64 Transfer type (TT) 72 Transmit 81, 87, 93, 97 TT 72 Q QECR 60 QMS 63 Queue Entry Control Register (QECR) 59, 60 Queue Mode Started (QMS) 63 U Update user default (UUD) 86 UUD 86 R V Receive 82, 90, 93, 98 Relative Humidity 100 Reliability 100 Report Network Statistics 67, 95 Reserved field (RSV) 75 Res
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