Datasheet

ManualsBrandsINTERSIL ManualsLinear ICsLinear IC - Op-amp CA 3130 E Multi-purpose PDIP 8

SEMICONDUCTOR

3-64

November 1996

CA3130, CA3130A

15MHz, BiMOS Operational Ampliﬁer

with MOSFET Input/CMOS Output

Features

• MOSFET Input Stage Provides:

- Very High Z

= 1.5 TΩ (1.5 x 10

Ω) (Typ)

- Very Low I

= 5pA (Typ) at 15V Operation

= 2pA (Typ) at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes

Negative Supply Rail; Input Terminals can be Swung

0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either

(or both) Supply Rails

Applications

• Ground-Referenced Single Supply Ampliﬁers

• Fast Sample-Hold Ampliﬁers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators

(Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Ampliﬁers

• Voltage Followers (e.g. Follower for Single-Supply D/A

Converter)

• Voltage Regulators (Permits Control of Output Voltage

Down to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectiﬁers

• Photo-Diode Sensor Ampliﬁers

Description

CA3130A and CA3130 are op amps that combine the

advantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors are

used in the input circuit to provide very-high-input

impedance, very-low-input current, and exceptional speed

performance. The use of PMOS transistors in the input stage

results in common-mode input-voltage capability down to

0.5V below the negative-supply terminal, an important

attribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the output volt-

age to within 10mV of either supply-voltage terminal (at very

high values of load impedance), is employed as the output

circuit.

The CA3130 Series circuits operate at supply voltages

ranging from 5V to 16V, (±2.5V to ±8V). They can be phase

compensated with a single external capacitor, and have ter-

minals for adjustment of offset voltage for applications

requiring offset-null capability. Terminal provisions are also

made to permit strobing of the output stage.

The CA3130A offers superior input characteristics over

those of the CA3130.

Pinouts

CA3131, CA3130A

(PDIP, SOIC)

TOP VIEW

CA3130, CA3130A

(METAL CAN)

TOP VIEW

OFFSET

INV.

NON-INV.

V-

STROBE

V+

OUTPUT

OFFSET

NULL

INPUT

NULL

TAB

OUTPUT

INV.

V- AND CASE

OFFSET

NON-INV.

OFFSET

STROBE

PHASE

COMPENSATION

NULL

INPUT

NULL

Ordering Information

PART NO.

(BRAND)

TEMP.

RANGE

(

C) PACKAGE

PKG.

NO.

CA3130AE

-55 to 125 8 Ld PDIP

E8.3

CA3130AM

(3130A)

-55 to 125 8 Ld SOIC

M8.15

CA3130AM96

(3130A)

-55 to 125 8 Ld SOIC (Note)

M8.15

CA3130AT

-55 to 125 8 Pin Metal Can

T8.C

CA3130BT

-55 to 125 8 Pin Metal Can

T8.C

CA3130E

-55 to 125 8 Ld PDIP

E8.3

CA3130M

(3130)

-55 to 125 8 Ld SOIC

M8.15

CA3130M96

(3130)

-55 to 125 8 Ld SOIC (Note)

M8.15

CA3130T

-55 to 125 8 Pin Metal Can

T8.C

NOTE: Denotes Tape and Reel.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 817.3

Summary of content (15 pages)

PAGE 1
CA3130, CA3130A S E M I C O N D U C T O R 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output November 1996 Features Description • MOSFET Input Stage Provides: - Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ) - Very Low II = 5pA (Typ) at 15V Operation = 2pA (Typ) at 5V Operation • Ideal for Single-Supply Applications • Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals can be Swung 0.
PAGE 2
CA3130, CA3130A Absolute Maximum Ratings Thermal Information DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . 16V Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . .
PAGE 3
CA3130, CA3130A Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC Unless Otherwise Specified PARAMETER SYMBOL Input Offset Voltage Adjustment Range TEST CONDITIONS 10kΩ Across Terminals 4 and 5 or 4 and 1 CA3130, CA3130A UNITS ±22 mV 1.5 TΩ Input Resistance RI Input Capacitance CI f = 1MHz 4.3 pF Equivalent Input Noise Voltage eN BW = 0.
PAGE 4
CA3130, CA3130A Schematic Diagram “CURRENT SOURCE LOAD” FOR Q11 CURRENT SOURCE FOR Q6 AND Q7 BIAS CIRCUIT Q1 Q2 7 V+ Q3 D1 Z1 8.3V D2 R1 D4 Q4 Q5 D3 40kΩ R 2 5kΩ SECOND STAGE INPUT STAGE NON-INV. INPUT D5 D6 (NOTE 5) D7 D8 OUTPUT STAGE 3 + INV.-INPUT 2 Q6 Q8 Q7 OUTPUT - 6 R4 1kΩ R3 1kΩ Q9 Q10 Q12 Q11 R5 1kΩ 5 R6 1kΩ OFFSET NULL 1 COMPENSATION 8 STROBING 4 V- NOTE: 5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.
PAGE 5
CA3130, CA3130A deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance. V+ CA3130 7 200µA 1.35mA 200µA BIAS CKT. 8mA (NOTE 5) 0mA (NOTE 7) Output Stage + 3 INPUT AV ≈ 6000X AV ≈ 5X AV ≈ 30X OUTPUT 6 2 - V4 5 CC 1 OFFSET NULL 8 STROBE COMPENSATION (WHEN REQUIRED) NOTES: 6.
PAGE 6
CA3130, CA3130A metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gate-protection network functions as if it is connected to Terminal 4 potential, and the Metal Can case of the CA3130 is also internally tied to Terminal 4, input Terminal 3 is essentially “guarded” from spurious leakage currents. INPUT VOLTAGE (V) 10 TA = 25oC 7.
PAGE 7
CA3130, CA3130A swung down to ground potential (or tied to ground), NMOS transistor Q12 is completely cut off and the supply-current to series-connected transistors Q8, Q12 goes essentially to zero. The two preceding stages in the CA3130, however, continue to draw modest supply-current (see the lower curve in Figure 20) even though the output stage is strobed off.
PAGE 8
CA3130, CA3130A Typical Applications Voltage Followers Operational amplifiers with very high input resistances, like the CA3130, are particularly suited to service as voltage followers. Figure 8 shows the circuit of a classical voltage follower, together with pertinent waveforms using the CA3130 in a split-supply configuration. A voltage follower, operated from a single supply, is shown in Figure 9, together with related waveforms.
PAGE 9
CA3130, CA3130A +15V +7.5V 0.01µF 0.01µF 7 3 + 2 - 3 7 + 10kΩ 10kΩ 6 6 - 2 2kΩ 4 4 8 1 0.01µF -7.5V CC = 56pF 1 25pF 8 56pF 2kΩ 5 100kΩ OFFSET ADJUST 2kΩ BW (-3dB) = 4MHz SR = 10V/µs 0.1µF 0.1µF Top Trace: Output Center Trace: Input FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV., 200ns/DIV.) FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL RAMPING (2V/DIV., 500µs/DIV.) Top Trace: Output Signal; 2V/Div., 5µs/Div. Center Trace: Difference Signa; 5mV/Div., 5µs/Div.
PAGE 10
CA3130, CA3130A 10V LOGIC INPUTS +10.010V LSB 9 8 7 6 3 10 14 11 6 5 4 3 2 MSB 1 6 3 10 6 3 10 BIT 1 2 3 4 5 6-9 2 CD4007A “SWITCHES” CD4007A “SWITCHES” CD4007A “SWITCHES” NOTE: All resistances are in ohms. 9 13 1 13 1 8 5 12 7 8 4 5 806K 1% 402K 1% 200K 1% 100K 1% 806K 1% 806K 1% +15V 1 12 8 5 (2) 806K 1% 806K 1% 750K 1% (4) 806K 1% (8) 806K 1% PARALLELED RESISTORS 10K 7 + OUTPUT +10.010V CA3085 CA3130 6 8 3 LOAD 22.
PAGE 11
CA3130, CA3130A 6VP-P INPUT; BW (-3dB) = 1.3MHz 6VP-P INPUT; BW (-3dB) = 360kHz +7.5V +7.5V 0.3VP-P INPUT; 0.3VP-P INPUT; BW (-3dB) = 240kHz 3 7 + CA3130 2 - 10kΩ 0.01µF BW (-3dB) = 320kHz 0.01µF +DC OUTPUT 7 3 + CA3130 2 - 10kΩ 6 6 1N914 1N914 4 -DC OUTPUT 4 100 kΩ + 100 kΩ 5µF - 2kΩ -7.5V FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT -7.5V FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT FIGURE 12.
PAGE 12
CA3130, CA3130A 2N3055 1Ω Q2 + + 10kΩ 2N2102 1kΩ CURRENT LIMIT ADJUST Q1 4.3kΩ 1W Q3 3.3kΩ 1W 2N5294 + +55V INPUT 43kΩ 1000pF 100µF - 2.2kΩ 1 5µF IC2 CA3086 Q4 + 8 - 2N2102 9 8, 7 3 5 Q3 Q1 Q2 6 ERROR AMPLIFIER 7 + 10, 11 1, 2 6 Q5 14 12 13 Q4 3 - 100µF OUTPUT: 0.1 TO 50V AT 1A 10kΩ CA3130 IC1 + 2 4 8.2kΩ 4 1kΩ 50kΩ 62kΩ VOLTAGE ADJUST - REGULATION (NO LOAD TO FULL LOAD): <0.005% INPUT REGULATION: 0.
PAGE 13
CA3130, CA3130A to adjust the circuit for slope symmetry of positive-going and negative-going signal excursions. +15V Another CA3130, IC3, is used as a controlled switch to set the excursion limits of the triangular output from the integrator circuit. Capacitor C2 is a “peaking adjustment” to optimize the high-frequency square-wave performance of the circuit. 0.
PAGE 14
CA3130, CA3130A +15V 0.01µF 14 1MΩ CA3600E (NOTE 12) 1µF QP1 2 QP2 11 QP3 7 750kΩ 3 + CA3130 2kΩ INPUT 2 6 13 1 3 10 - 500µF 1µF 8 6 12 4 RL = 100Ω (PO = 150mW AT THD = 10%) 8 AV(CL) = 48dB 5 QN1 LARGE SIGNAL BW (-3 dB) = 50kHz QN2 7 QN3 4 9 510kΩ NOTES: 11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130. 12. See file number 619. FIGURE 17.
PAGE 15
CA3130, CA3130A Typical Performance Curves 14 ∞ LOAD RESISTANCE = TA = 25oC OUTPUT VOLTAGE BALANCED = V+/2 V- = 0 12.5 QUIESCENT SUPPLY CURRENT (mA) QUIESCENT SUPPLY CURRENT (mA) 17.5 (Continued) 10 7.5 5 OUTPUT VOLTAGE HIGH = V+ OR LOW = V2.5 25oC 8 125oC 6 4 2 0 6 8 10 12 14 16 18 0 2 10 10V 15V POSITIVE SUPPLY VOLTAGE = 5V 1 0.1 0.01 0.001 0.001 0.01 0.1 1.0 6 8 10 12 14 16 FIGURE 21.