Datasheet

ManualsBrandsIntersil ManualsDriversFull Bridge N Channel FET Driver PDIP

November 1996

HIP4081

80V/2.5A Peak, High Frequency

Full Bridge FET Driver

Features

• Independently Drives 4 N-Channel FET in Half Bridge

or Full Bridge Conﬁgurations

• Bootstrap Supply Max Voltage to 95V

• Drives 1000pF Load at 1MHz in Free Air at 50

C with

Rise and Fall Times of Typically 10ns

• User-Programmable Dead Time

• On-Chip Charge-Pump and Bootstrap Upper Bias

Supplies

• DIS (Disable) Overrides Input Control

• Input Logic Thresholds Compatible with 5V to 15V

Logic Levels

• Very Low Power Consumption

Applications

• Medium/Large Voice Coil Motors

• Full Bridge Power Supplies

• Class D Audio Power Ampliﬁers

• High Performance Motor Controls

• Noise Cancellation Systems

• Battery Powered Vehicles

• Peripherals

• U.P.S.

Description

The HIP4081 is a high frequency, medium voltage Full

Bridge N-Channel FET driver IC, available in 20 lead plastic

SOIC and DIP packages. The HIP4081 can drive every pos-

sible switch combination except those which would cause a

shoot-through condition. The HIP4081 can switch at fre-

quencies up to 1MHz andssssss is well suited to driving

Voice Coil Motors, high-frequency Class D audio ampliﬁers,

and power supplies.

For example, the HIP4081 can drive medium voltage brush

motors, and two HIP4081s can be used to drive high perfor-

mance stepper motors, since the short minimum “on-time”

can provide ﬁne micro-stepping capability.

Short propagation delays of approximately 55ns maximizes

control loop crossover frequencies and dead-times which

can be adjusted to near zero to minimize distortion, resulting

in rapid, precise control of the driven load.

A similar part, the HIP4080, includes an on-chip input com-

parator to create a PWM signal from an external triangle

wave and to facilitate “hysteresis mode” switching.

See Application Note AN9325 for HIP4081, document

#9325. Intersil web home page: http://www.intersil.com

Similar part HIP4081A includes undervoltage circuitry which

does not require the circuitry shown in Figure 30 of this data

sheet.

Pinout

HIP4081

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART

NUMBER

TEMP.

RANGE (

C) PACKAGE

PKG.

NUMBER

HIP4081IP -40 to 85 20 Lead Plastic DIP E20.3

HIP4081IB -40 to 85 20 Lead Plastic SOIC M20.3

BHB

BHI

DIS

BLI

ALI

HDEL

AHI

LDEL

AHB

BHO

BLO

BLS

BHS

ALS

ALO

AHS

AHO

File Number 3556.7

[ /Title

(HIP40

81)

/Sub-

ject

(80V/2

.5A

Peak,

High

Fre-

quency

Full

Bridge

FET

Driver)

/Autho

r ()

/Key-

words

(Inter-

sil

Corpo-

ration,

Semi-

con-

ductor,

HIP40

8X,

full

bridge,

H-

bridge,

con-

ﬁgura-

tion,

driver,

pre-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Summary of content (18 pages)

PAGE 1
[ /Title (HIP40 81) /Subject (80V/2 .5A Peak, High Frequency Full Bridge FET Driver) /Autho r () /Keywords (Intersil Corporation, Semiconductor, HIP40 8X, full bridge, H bridge, Hbridge, configuration, driver, pre- HIP4081 80V/2.
PAGE 2
HIP4081 Application Block Diagram 80V 12V BHO BHS BHI LOAD BLO BLI HIP4081 ALI ALO AHS AHI AHO GND GND Functional Block Diagram (1/2 HIP4081) HIGH VOLTAGE BUS ≤ 80VDC AHB 10 CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 7 CBS AHS VDD 16 AHI AHO 11 12 TURN-ON DELAY DBS DIS 3 15 DRIVER ALI 6 TURN-ON DELAY VCC ALO 13 ALS 14 HDEL 8 LDEL 9 VSS 4 TO VDD (PIN 16) 2 CBF +12VDC BIAS SUPPLY
PAGE 3
HIP4081 Typical Application (PWM Mode Switching) 80V 1 BHB BHO 20 12V 2 BHI BHS 19 DIS 3 DIS BLO 18 4 VSS BLS 17 5 BLI VDD 16 PWM INPUT 6 ALI VCC 15 7 AHI ALS 14 8 HDEL ALO 13 9 LDEL AHS 12 10 AHB AHO 11 LOAD 12V GND - TO OPTIONAL CURRENT CONTROLLER + 6V GND 3
PAGE 4
HIP4081 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . VAHS, BHS -0.
PAGE 5
HIP4081 Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) TJ = 25oC PARAMETER SYMBOL TEST CONDITIONS TJS = -40oC TO 125oC MIN TYP MAX MIN MAX UNITS Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A Peak Pulldown Current IO- VOUT = 12V 1.7 2.4 3.3 1.3 3.
PAGE 6
HIP4081 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20).
PAGE 7
HIP4081 Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL THPHL DIS = 0 XLI XHI XLO XHO THPLH TLPLH FIGURE 1. TR (10% - 90%) INDEPENDENT MODE DIS = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO FIGURE 2. BISTATE MODE TDLPLH DIS TDIS TREF-PW XLI XHI XLO XHO THEN FIGURE 3.
PAGE 8
HIP4081 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified 11.0 10.5 12.0 SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 14.0 10.0 8.0 6.0 10.0 9.5 9.0 8.5 4.0 8.0 2.0 6 8 10 12 14 0 100 200 VDD SUPPLY VOLTAGE (V) 400 500 600 700 800 900 1000 FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) 5.0 30.
PAGE 9
HIP4081 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 80 PROPAGATION DELAY (ns) NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) 15.0 14.0 13.0 12.0 11.0 10.0 -40 -20 0 20 40 60 80 100 70 60 50 40 30 -40 120 -20 0 FIGURE 10.
PAGE 10
HIP4081 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, 80 80 70 70 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 60 50 40 30 20 -40 -20 0 20 40 60 80 JUNCTION TEMPERATURE (oC) 100 50 40 30 20 -40 120 FIGURE 16.
PAGE 11
HIP4081 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 1500 1250 5.5 VCC - VOH (mV) HDEL, LDEL INPUT VOLTAGE (V) 6.0 5.0 1000 -40oC 750 0oC 500 25oC 4.5 75oC 250 125oC 4.0 -40 -20 0 20 40 60 80 100 0 120 6 8 JUNCTION TEMPERATURE (oC) FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE 12 14 FIGURE 23.
PAGE 12
HIP4081 Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 150 1000 120 200 DEAD-TIME (ns) LEVEL-SHIFT CURRENT (µA) 500 100 50 20 10 80V 5 60V 90 60 30 40V 2 20V 1 0 1 2 5 10 20 50 100 200 10 500 1000 50 100 150 200 250 HDEL/LDEL RESISTANCE (kΩ) SWITCHING FREQUENCY (kHz) FIGURE 29. MINIMUM DEAD-TIME vs DEL RESISTANCE FIGURE 28.
PAGE 13
IN2 IN1 POWER SECTION +12V B+ Q1 1 2 U2 R29 JMPR1 + C6 JMPR5 CONTROL LOGIC SECTION JMPR2 12 U2 4 V SS 5 OUT/BLI 6 IN+/ALI IN+/ALI CD4069UB JMPR4 2 13 CW CD4069UB 9 LDEL 10 AHB R34 3 IN-/AHI DD 3 L1 AO Q2 2 +12V R23 L2 C1 1 BO C2 3 ALO 13 AHS 12 Q4 R24 AHO 11 2 1 3 CW 3 CR1 2 1 R22 VCC 15 ALS 14 7 IN-/AHI 8 HDEL R33 10 U2 BLS 17 16 V 2 1 1 C3 CX CY R30 R31 C5 ENABLE IN I R32 3 U2 4 ALS 15K 9 U2 8 COM O CD4069UB HIP4081 11 Q3 3 C4 1 BHB B
PAGE 14
C1 R26 COM C8 C6 R28 R27 B+ CR2 AO + R32 + JMPR5 +12V C7 R29 GND Q1 C4 BHO U1 Q3 1 R22 1 ALS ALO Q4 1 1 R21 LDEL CY CX FIGURE 32.
PAGE 15
HIP4081 Supplemental Information for HIP4080 and HIP4081 Power Application level of 1.7V while VDD/VCC is ramping up, so that shoot through is avoided. After power is up the chip can be enabled by the ENABLE signal which pulls the DIS pin low. The HIP4080 and HIP4081 H-Bridge Driver ICs require external circuitry to assure reliable start-up conditions of the upper drivers.
PAGE 16
HIP4081 Timing Diagrams VDD 12V, FINAL VALUE 8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE) VDD 12V, FINAL VALUE DIS 8.5V TO 10.5V (ASSUMES 5% RESISTORS) ALI, BLI LDEL 5.1V DIS t1 1.7V NOTE: =10ms t2 NOTE: 6. ALI and/or BLI may be high after t1, whereupon the ENABLE pin may also be brought high. 7. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin to go through one complete cycle (transition order is not important).
PAGE 17
HIP4081 Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 D 0.980 1.060 24.89 D1 0.
PAGE 18
HIP4081 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.