ISM14585-L35 Specification ISM14585-L35 BLE 5.0 SiP Preliminary Data Sheet 5.0 BLE + Cortex M0 + PMU + PA + Flash DOC-DS-14585-201807-3.
ISM14585-L35 Specification Table of Contents 1 PART NUMBER DETAIL DESCRIPTION .......................................................................... 5 1.1 Ordering Information ...................................................................................................... 5 1.2 Ordering Information Configuration............................................................................... 5 2 OVERVIEW .............................................................................................
ISM14585-L35 Specification 9.5.3 DMA CHANNEL OPERATION ............................................................................. 26 9.5.4 DMA ARBITRATION ............................................................................................. 27 9.5.5 FREEZING DMA CHANNELS............................................................................... 28 9.6 I2C Interface ................................................................................................................. 28 9.
ISM14585-L35 Specification 10 MECHANICAL SPECIFICATION ..................................................................................... 94 10.1 Size of the Module ........................................................................................................ 94 10.2 Mechanical Dimension ................................................................................................. 94 11 Recommend Footprint (Board Design) .....................................................................
ISM14585-L35 Specification 1 PART NUMBER DETAIL DESCRIPTION 1.1 Ordering Information Device ISM14585 Module Supports both Internal Antenna or w.fl External Antenna options. ISM14585-EVB Internal Antenna Evaluation Board ISM14585-EVB-W w.fl External Antenna Evaluation Board Description BLE 5.0 + Cortex M0 Module with integrated PMU, PA, 8Mb of Flash and internal antenna BLE 5.0 + Cortex M0 Module with integrated PMU, PA, 8Mb of Flash and internal antenna EVB (Evaluation Board) BLE 5.
ISM14585-L35 Specification 2 OVERVIEW The Inventek Systems ISM14585-L35 SiP (System in Package), is the smallest, lowest power and most integrated Bluetooth® 5.0 solution available. The ISM14585-L35 platform is the first BLE module from Inventek's FLEXiBLE product family. The ISM14585-L35 SiP is an embedded wireless Bluetooth Low Energy (BLE) IoT radio, based on the Dialog Semiconductor DA14585 radio SoC (System on Chip).
ISM14585-L35 Specification The ISM14585-L35 is easy to design-in and supports standalone as well as hosted applications. The ISM14585-L35 is supported by a complete development environment with Dialog’s SmartSnippets™ software that helps customers optimize software for power consumption. The ISM14585-L35 supports several fully qualified profiles embedded in ROM (see “Typical Applications” below), and the option of loading additional profiles into RAM. The low cost, small foot print (6.0mm x 8.6mm x 1.
ISM14585-L35 Specification 3.1 Feature Highlights: • • • • • • • • • • • Frequency Band: 2.4GHz Complies to the Bluetooth 5 core specification Supports up to 8 Bluetooth LE connections Network Standard: Bluetooth Low Energy Longest battery life Operating voltage 3.3V Operating Temperature: -40℃ to 85℃ MSL level 3 Low system Bill of Materials FCC, CE, IE and Japan certification in-process Certifications will comply with Bluetooth V5.
ISM14585-L35 Specification • • • • Digital interfaces o Gen. Purpose I/Os: 14 o 2 x UARTs with hardware flow control up to 1 MBd o SPI+™ interface o I2C bus at 100 kHz, 400 kHz o 3-axes capable Quadrature Decoder o I2S and PDM audio interface Analog interfaces o 4-channel 10-bit ADC Radio transceiver o Fully integrated 2.4 GHz CMOS transceiver o Single wire antenna: no RF matching, or RX/TX switching required o Supply current at VBAT3V: ▪ TX: 3.4 mA ▪ RX: 3.
ISM14585-L35 Specification 3.3 Key Benefits • • • Lowest power consumption Smallest system size Lowest system cost 3.4 Limitations Inventek Systems products are not authorized for use in safety-critical applications (such as life support) where a failure of the Inventek Systems product would reasonably be expected to cause severe personal injury or death. 3.
ISM14585-L35 Specification FCC and IC Regulatory Information Model (HVIN): ISM14585-L35-P8 Product Marketing Name (PMN): ISM14585 FCC ID: 07P-14585 IC: 10147A-14585 This module is limited to OEM installation only. OEM integrators must ensure that the end-user has no manual instructions to remove or install the module. OEM’s must comply with FCC marking regulation part 15 declaration of conformity (Section 2.925(e)).
ISM14585-L35 Specification NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
ISM14585-L35 Specification par Industrie Canada. Pour rѐ duire le risqué d’interference aux autres utilisateures, le type d’antenne et son gain doivent être choisis de maniѐ re que la puissance isotrpe rayonnѐ e ѐ quivalente (PIRE) ne dѐ passe pas ce qui est nѐ cessaire pour une communication rѐ ussie. The radio transmitter has been approved by Industry Canada to operate with the antenna types listed above with the maximum permissible gain and required antenna impedance for each antenna type indicated.
ISM14585-L35 Specification 4 COMPLEMENTARY DOCUMENTATION 4.1 EVB ➢ The Inventek ISM14585-L35 Evaluation Board is the ISM14585-L35-EVB ➢ Please reference the ISM14585-L35-EVB User’s Manual o Evaluation Board Specification o EVB User’s Guide o Design Guidelines 5 ISM14585-L35 SoC & Module BLOCK DIAGRAMS 5.1 ISM14585-L35 SoC Block Diagram: DIALOG DA14585 Radio w/Audio I/F SoC: Figure 1 Dialog DA14585 SoC Block Diagram DOC-DS-14585-201807-3.
ISM14585-L35 Specification 5.2 ISM14585-L35 Module Block Diagram Configuration Options: • • • • UART: Universal synchronous/asynchronous receiver transmitters SPI: Serial Peripheral Interface GPIO: General-purpose input/output SWD: Serial Wire Debug DOC-DS-14585-201807-3.
ISM14585-L35 Specification 6 Electrical Specification 6.1 Absolute Maximum Rating Supply Power Storage Temperature Voltage ripple Max +4 Volt - 40° to 125° Celsius +/- 2% Max. Values not exceeding Operating voltage min Max 3.6 Power BT_VBAT Power Supply Absolute Maximum Ratings VDD_PA - 3.6 VDD_FLASH - 3.6 VSS-0.3 VBAT+0.3 Voltage on input or output pin 6.2 Recommendable Operation Condition 6.2.
ISM14585-L35 Specification 6.3 Current Consumption 6.3.1 BLUETOOTH LOW ENERGY Condition: Condition: 25deg.C Item Condition Tx Mode Transmitter and baseband are both operating, 100% Receiver and baseband are both operating, 100% RX Mode Min Nom TBD Max Unit mA mA TBD 7 RF Specification 7.1 RF Transmitter Specification 7.1.1 BLE RF SPECIFICATION Parameter Frequency Range RX sensea TX Power Mod char: delta f1 average Mod char: delta f2 maxc Mod char: ratio • • • • Mode and Condition LE GFSK, 0.
ISM14585-L35 Specification 8 Pin Definition Figure 3. TOP VIEW 8.1 Module Pin Out Schematic (Internal Antenna configuration) DOC-DS-14585-201807-3.
ISM14585-L35 Specification 8.2 Detail Pin definition information Please reference the Dialog DA14585 Bluetooth 5.0 SoC with Audio Interface Data Sheet for any additional information. Pin Name Pin Number I/O Type Description Radio BT_RF 34 I/O RF I/O antenna port 35 I/O Embedded Antenna Port. Enable: tie to BT_RF pin Disable: tie to GND when not use.
ISM14585-L35 Specification Pin Name Pin Number I/O Type Description Digital I/O P0_0 (Note2) 18 P0_1 (Note2) 29 P0_2 (Note2) 30 P0_3 (Note2) 17 P0_4 (Note2) 23 P0_5 (Note2 & 3) 21 P0_6 (Note2) 20 P1_2 (Note 1 & 2) 13 P1_3 (Note 1 & 2) 14 DIO / ADC 0 / INPUT/OUTPUT with selectable pull up/down resistor. Pulldown enabled during and after reset. General purpose I/O port bit or SPI CLK alternate function nodes. Contains state retention mechanism during power down.
ISM14585-L35 Specification 9 Addition Information 9.1 Microcontroller Unit The ISM14585-L35 includes a Cortex-M0 32-bit Reduced Instruction Set Computing (RISC) processor with a von Neumann architecture (single bus interface). It uses an instruction set called Thumb, which was first supported in the ARM7TDMI processor. However, several newer instructions from the ARMv6 architecture and a few instructions from the Thumb-2 technology are also included.
ISM14585-L35 Specification 9.2 Buck Power Configuration The ISM14585 module is configured for Buck mode only and the “Switch” Pin requires the Synchronous DC-DC converter to be configured for 3.3V or higher. 9.3 ANTENNA CONFIGURATION OPTIONS 9.3.1 Integrated Antenna ▪ ▪ Pin 34 is connected to Pin 35. Please reference the ISM14585-L35-P8-EVB Evaluation Board User’s Manual for Layout specification. 9.3.2 External w.fl Antenna ▪ ▪ Pin 34 is connected to a w.fl external antenna connector.
ISM14585-L35 Specification 9.4 External Reset The ISM14585-L35 comprises an RST pad which is active high. It contains an RC filter for spikes suppression with 400kΩ and 2.8pF for the resistor and the capacitor respectively. It also contains a 25kΩ pull-down resistor. This pad should be connected to ground if not needed by the application. The response is illustrated in the Figure 4 which displays the voltage (V) on the vertical axis and the time (μs) on the horizontal axis:. Figure 4.
ISM14585-L35 Specification 1. The PWR-On reset which is triggered by a GPIO set as POR source with selectable polarity and/or the RST pad after a programmable time delay. 2. The HW reset which is basically triggered by the RST pad when it becomes active for a short period of time (less than the programmable delay for POR). 3. The SW reset which is triggered by writing the SYS_CTRL_REG[SW_RESET] bit.
ISM14585-L35 Specification Reset by POR Only Reset by POR or HW Reset BANDGAP_REG POR_PIN_REG POR_TIMER_REG RF registers containing the trimming values for the VCO, the LNA and the I/O capacitance OTPC_NWORDS_REG CLK_FREQ_TRIM_REG CLK_RADIO_REG All RF calibration registers BLE_CNTL2_REG CLK_CTRL_REG PMU_CTRL_REG SYS_CTRL_REG CLK_32K_REG_I CLK_16M_REG_I CLK_RCX32K_REG TRIM_CTRL_REG DEBUG_REG[DEBUGS_FREEZE_EN] GP_CONTROL_REG[EM_MAP] Reset by POR, HW or SW Reset The rest of the Register File 9.4.
ISM14585-L35 Specification 9.4.2.1 POR TIMER CLOCK The Power-On Reset timer is clocked by the RC32k clock. If the application disables the RC32k, then the hardware takes care of enabling the RC32k clock when the POR source (Reset pad or GPIO) is asserted. It should be noted that if POR is generated from the Reset pad the RC32 will operate with the reset trimming value. If a GPIO is used as POR source, the RC32 clock will be trimmed.
ISM14585-L35 Specification 9.4.2.5 POWER-ON RESET CONSIDERATIONS If any of the POR sources is asserted then the POR timer starts to count. When a POR source is released before the timer has expired, POR timer will reset to 0. If a second source is asserted while the first is already asserted and the first is released after that point, POR will occur; assuming that the total time of both sources kept asserted is larger or equal than the POR_TIME.
ISM14585-L35 Specification Figure 7 DMA Controller Block Diagram 9.5.1 DMA PERIPHERALS The list of peripherals that can request for a DMA service is presented in below table Name SPI SPI UART UART UART2 UART2 I2C I2C PCM PCM SRC SRC Direction RX TX RX TX RX TX RX TX RX TX RX TX DOC-DS-14585-201807-3.
ISM14585-L35 Specification 9.5.2 INPUT/OUTPUT MULTIPLEXER The multiplexing of peripheral requests is controlled by DMA_REQ_MUX_REG. Thus, if DMA_REQ_MUX_REG [DMAxy_SEL] is set to a certain (non-reserved) value, the TX/RX request from the corresponding peripheral will be routed to DMA channels y (TX request) and x (RX request) respectively. Similarly, an acknowledging de-multiplexing mechanism is applied.
ISM14585-L35 Specification Figure 8 DMA Channel Diagram If at the end of a DMA cycle, the DMA start condition is still true, the DMA continues. The DMA stops if DREQ_MODE is low or if DMAx_LEN_REG is equal to the internal index register. This condition also clears the DMA_ON bit. If bit CIRCULAR is set to 1, the DMA controller automatically resets the internal index registers and continues from its starting address without intervention of the ARM CortexTM M0.
ISM14585-L35 Specification requests DMA. If two or more channels have the same priority, an inherent priority applies, (see register description). With DREQ_MODE = 0, a DMA can be interrupted by a channel with a higher priority if the DMA_IDLE bit is set. When DMA_INIT is set, however, the DMA channel currently performing the transfer locks the bus and cannot be interrupted by any other channel, until the transfer is completed, regardless if DMA_IDLE is set.
ISM14585-L35 Specification • • • • • • • • • • • • • Two-wire I2C serial interface consists of a serial data line (SDA) and a serial clock (SCL) Two speeds are supported: o Standard mode (0 to 100kbit/s) o Fast mode (<= 400kbit/s) Clock synchronization 32B deep transmit/receive FIFOs Master transmit, Master receive operation 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers Bulk transmit mode Default slave address of 0x055 Interrupt or polled-mode operation Handles Bit and Byte waiting
ISM14585-L35 Specification • • • • • • • o Check for bus idle o Generate a START and a STOP o Setup the data and hold the data Rx Shift: Takes data into the design and extracts it in byte format. Tx Shift: Presents data supplied by CPU for transfer on the I2C bus. Rx Filter: Detects the events in the bus; for example, start, stop and arbitration lost. Toggle: Generates pulses on both sides and toggles to transfer signals across clock domains.
ISM14585-L35 Specification Figure 10 Master/Slave and Transmitter/Receiver Relationships • Multi-master. The ability for more than one master to co-exist on the bus at the same time without collision or data loss. • Arbitration. The predefined procedure that authorizes only one master at a time to take control of the bus. For more information about this behavior, refer to Multiple Master Arbitration section. • Synchronization.
ISM14585-L35 Specification 9.7.1.1BUS TRANSFER TERMS The following terms are specific to data transfers that occur to/from the I2C bus: • START (RESTART). Data transfer begins with a START or RESTART condition. The level of the SDA data line changes from high to low, while the SCL clock line remains high. When this occurs, the bus becomes busy. • STOP. Data transfer is terminated by a STOP condition.
ISM14585-L35 Specification master then acknowledges the transaction with the ACK pulse. This transaction continues until the master terminates the transmission by not acknowledging (NACK) the transaction after the last byte is received, and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition. This behavior is illustrated in Figure 11. Figure 11 Data Transfer on the I2C Bus The I2C is a synchronous serial interface.
ISM14585-L35 Specification 9.7.2.2 COMBINED FORMATS The I2C Controller supports mixed read and write combined format transactions in both 7-bit and 10-bit addressing modes. The I2C Controller does not support mixed address and mixed address format - that is, a 7-bit address transaction followed by a 10-bit address transaction or vice versa combined format transactions. To initiate combined format transfers, I2C_CON.I2C_RESTART_EN should be set to 1.
ISM14585-L35 Specification Figure 12 START and STOP Conditions Note: The signal transitions for the START/STOP conditions, as depicted in Figure 12, reflect those observed at the output signals of the Master driving the I2C bus. Care should be taken when observing the SDA/SCL signals at the input signals of the Slave(s), because unequal line delays may result in an incorrect SDA/SCL timing relationship. 9.7.3.
ISM14585-L35 Specification 10-bit Address Format During 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte contains the following bit definition. The first five bits (bits 7:3) notify the slaves that this is a 10-bit transfer followed by the next two bits (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (bit 0) is the R/W bit. The second byte transferred sets bits 7:0 of the slave address.
ISM14585-L35 Specification 9.7.3.3TRANSMITTING AND RECEIVING PROTOCOLS The master can initiate data transmission and reception to/from the bus, acting as either a master-transmitter or master-receiver. A slave responds to requests from the master to either transmit data or receive data to/from the bus, acting as either a slavetransmitter or slave-receiver, respectively.
ISM14585-L35 Specification that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the No Acknowledge (NACK) so that the master can issue a STOP condition. When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART condition. This is identical to a START condition except it occurs after the ACK pulse. The master can then communicate with the same slave or a different slave.
ISM14585-L35 Specification Figure 17 START BYTE Transfer The START BYTE procedure is as follows: 1. Master generates a START condition. 2. Master transmits the START byte (0000 0001). 3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on the bus) 4. No slave sets the ACK signal to 0. 5. Master generates a RESTART (R) condition.
ISM14585-L35 Specification For high-speed mode, the arbitration cannot go into the data phase because each master is programmed with a unique high-speed master code. This 8-bit code is defined by the system designer and is set by writing to the High Speed Master Mode Code Address Register, I2C_HS_MADDR. Because the codes are unique, only one master can win arbitration, which occurs by the end of the transmission of the high-speed master code.
ISM14585-L35 Specification 9.7.5 CLOCK SYNCHRONIZATION When two or more masters try to transfer information on the bus at the same time, they must arbitrate and synchronize the SCL clock. All masters generate their own clock to transfer messages. Data is valid only during the high period of SCL clock. Clock synchronization is performed using the wired-AND connection to the SCL signal.
ISM14585-L35 Specification 9.7.6.1 SLAVE MODE OPERATION This section includes the following procedures: • Initial Configuration • Slave-Transmitter Operation for a Single Byte • Slave-Receiver Operation for a Single Byte • Slave-Transfer Operation for Bulk Transfers Initial Configuration To use the I2C Controller as a slave, perform the following steps: 1. Disable the I2C Controller by writing a ‘0’ to bit 0 of the I2C_ENABLE register. 2. Write to the I2C_SAR register (bits 9:0) to set the slave address.
ISM14585-L35 Specification 3. The I2C Controller asserts the RD_REQ interrupt (bit 5 of the I2C_RAW_INTR_STAT register) and holds the SCL line low. It is in a wait state until software responds. If the RD_REQ interrupt has been masked, due to I2C_INTR_MASK[5] register (M_RD_REQ bit field) being set to 0, then it is recommended that a hardware and/or software timing routine be used to instruct the CPU to perform periodic reads of the I2C_RAW_INTR_STAT register. a.
ISM14585-L35 Specification 8. If the RD_REQ and/or TX_ABRT interrupts have been masked, then clearing of the I2C_RAW_INTR_STAT register will have already been performed when either the R_RD_REQ or R_TX_ABRT bit has been read as 1. 9. The I2C Controller releases the SCL and transmits the byte. 10. The master may hold the I2C bus by issuing a RESTART condition or release the bus by issuing a STOP condition.
ISM14585-L35 Specification (RD_REQ) from the remote master (master-receiver), at a minimum there should be at least one entry placed into the slave-transmitter’s TX FIFO. The I2C Controller is designed to handle more data in the TX FIFO so that subsequent read requests can take that data without raising an interrupt to get more data.
ISM14585-L35 Specification transferred to the processor bus clock domain where the FIFO exists and the contents of the TX FIFO is cleared at that time. 9.7.6.2 MASTER MODE OPERATION This section includes the following topics: • Initial Configuration • Master Transmit and Master Receive Initial Configuration The procedures are very similar and are only different with regard to where the I2C_10BITADDR_MASTER bit is set (either bit 4 of I2C_CON register or bit 12 of I2C_TAR register).
ISM14585-L35 Specification 6. Enable the I2C Controller by writing a 1 in bit 0 of the I2C_ENABLE register. 7. Now write transfer direction and data to be sent to the I2C_DATA_CMD register. If the I2C_DATA_CMD register is written before the I2C Controller is enabled, the data and commands are lost as the buffers are kept cleared when I2C Controller is disabled. 8. This step generates the START condition and the address byte on the I2C Controller.
ISM14585-L35 Specification 1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling period for the highest I2C transfer speed used in the system and supported by I2C Controller. For example, if the highest I2C transfer mode is 400kbit/s, then this ti2c_poll is 25 μs. 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any repeated polling operation exceeds this maximum value, an error is reported. 3.
ISM14585-L35 Specification • • • Line break generation and detection Prioritized interrupt identification Programmable serial data baud rate as calculated by the following: baud rate = (serial clock frequency)/(divisor). Figure 20 UART Block Diagram 9.8.1 UART (RS232) SERIAL PROTOCOL Because the serial communication between the UART and the selected device is asynchronous, additional bits (start and stop) are added to the serial data to indicate the beginning and end.
ISM14585-L35 Specification An additional parity bit may be added to the serial character. This bit appears after the last data bit and before the stop bit(s) in the character structure to provide the UART with the ability to perform simple error checking on the received data. The UART Line Control Register (UART_LCR_REG) is used to control the serial character characteristics. The individual bits of the data word are sent after the start bit, starting with the least significant bit (LSB).
ISM14585-L35 Specification The data format is similar to the standard serial (sout and sin) data format. Each data character is sent serially, beginning with a start bit, followed by 8 data bits, and ending with at least one stop bit. Thus, the number of data bits that can be sent is fixed. No parity information can be supplied and only one stop bit is used while in this mode. Trying to adjust the number of data bits sent or enable parity with the Line Control Register (LCR) has no effect.
ISM14585-L35 Specification It should be noted that for all sclk frequencies greater than or equal to 7.37MHz (and obey the requirements of the Low Power Divisor Latch registers), pulses of 1.41μs are detectable. However, there are several values of sclk that do not allow the detection of such a narrow pulse and these are as follows: Table: Low Power Divisor Latch Register Values: SCLK 1.84 MHz 3.69 MHz 5.33 MHz Low Power Divisor Latch Register Value 1 2 3 Min Pulse Width for Detection 3.77 μs 2.
ISM14585-L35 Specification • • • • Receiver Error Receiver Data Available Character Timeout (in FIFO mode only) Transmitter Holding Register Empty at/below threshold (in Programmable THRE interrupt mode) When an interrupt occurs, the master accesses the UART_IIR_REG to determine the source of the interrupt before dealing with it accordingly.
ISM14585-L35 Specification Figure 24 Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode This threshold level is programmed into FCR[5:4]. The available empty thresholds are: empty, 2, ¼ and ½. See UART_FCR_REG for threshold setting details. Selection of the best threshold value depends on the system's ability to begin a new transmission sequence in a timely manner.
ISM14585-L35 Specification or FIFO). The flowchart of THRE interrupt generation when not in programmable THRE interrupt mode is shown in Figure 25. Figure 25 Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode 9.8.6 SHADOW REGISTERS The shadow registers shadow some of the existing register bits that are regularly modified by software. These can be used to reduce the software overhead that is introduced by having to perform read-modify-writes.
ISM14585-L35 Specification • UART_STER_REG accesses the FCR[5-4] register without accessing the other UART_FCR_REG bits. 9.8.7 DIRECT TEST MODE The on-chip UARTS can be used for the Direct Test Mode required for the final product PHY layer testing. It can be done either over the HCI layer, which engages a full CTS/RTS UART or using a 2- wire UART directly as described in the Bluetooth Low Energy Specification (Volume 6, Part F). 9.
ISM14585-L35 Specification Figure 26 SPI Block Diagram 9.9.1 OPERATION WITHOUT FIFOS This mode is the default mode. Master Mode To enable SPITM operation, first the individual port signal must be enabled. Next the SPI must be configured in SPI_CTRL_REG, for the desired mode. Finally bit SPI_ON must be set to 1. A SPI transfer cycle starts after writing to the SPI_RX_TX_REG0. In case of 32 bits mode, the PI_RX_TX_REG1 must be written first. Writing to SPI_RX_TX_REG0 also sets the SPI_TXH.
ISM14585-L35 Specification SPI_INT_PEND bit in (RE)SET_INT_PENDING_REG is set. The received bits in the IO buffer are copied to the SPI_RX_TX_REG0 (and SPI_RX_TX_REG1 in case of 32 bits mode) were they can be read by the CPU. Interrupts to the CPU can be disabled using the SPI_MINT bit. To clear the SPI interrupt source, any value to SPI_CLEAR_INT_REG must be written. Note however that SPI_INT will be set as long as the RX-FIFO contains unread data.
ISM14585-L35 Specification Writes Only Mode In “writes only” mode (SPI_FIFO_MODE = “10“) only the TX-FIFO is used. Received data will be copied to the SPI_RX_TX_REGx, but if a new SPI transfer is finished before the old data is read from the memory, this register will be overwritten. SPI_INT acts as a tx_request signal, indicating that there is still place in the FIFO. It will be ‘0’ when the FIFO is full or else ‘1’ when it’s not full.
ISM14585-L35 Specification Figure 27 SPI Master/Slave, Mode 0: SPI_POL=0 and SPI_PHA=0 Note 1: If 9 bits SPI mode, the MSB bit in transmit direction is determined by bit SPI_CTRL_REG[SPI_9BIT_VAL]. In receive direction, the MSB is received but not stored. Figure 28 SPI Master/Slave, Mode 1: SPI_POL=0 and SPI_PHA=1 For the MSB bit refer to Note 1 DOC-DS-14585-201807-3.
ISM14585-L35 Specification Figure 29 SPI Master/Slave, Mode 2: SPI_POL=1 and SPI_PHA=0 For the MSB bit refer to Note 1. Figure 30 SPI Master/slave, Mode 3: SPI_POL=1 and SPI_PHA=1 For the MSB bit refer to Note 1 DOC-DS-14585-201807-3.
ISM14585-L35 Specification 9.10 Wake-Up Timer The Wake-up timer can be programmed to wake up the ISM14585 from power down mode after a pre-programmed number of GPIO events. Each of the GPIO inputs can be selected to generate an event by programming the corresponding WKUP_SELECT_Px_REG register. When all WKUP_SELECT_Px_REG registers are configured to generate a wake-up interrupt, a toggle on any GPIO will wake up the system.
ISM14585-L35 Specification The event counter is edge sensitive. After detecting an active edge, a reverse edge must be detected first before it goes back to the IDLE state and from there starts waiting for a new active edge. If the event counter is equal to the value set in the WKUP_COMPARE_REG register, the counter will be reset, and an interrupt will be generated, if it was enabled by WKUP_CTRL_REG[ENABLE_IRQ]. The interrupt can be cleared by writing any value to register WKUP_RESET_IRQ_REG.
ISM14585-L35 Specification 9.11.1 TIMER 0 Timer 0 is a 16-bit general purpose software programmable timer, which has the ability of generating Pulse Width Modulated signals, namely PWM0 and PWM1. It also generates the SWTIM_IRQ interrupt to the ARM Cortex-M0. It can be configured in various modes regarding output frequency, duty cycle and the modulation of the PWM signals.
ISM14585-L35 Specification Figure 33 Timer 0 Block Diagram Figure 33 shows the block diagram of Timer 0. The 16 bits timer consists of two counters: T0-counter and ON-counter, and three registers: TIMER0_RELOAD_M_REG, TIMER0_RELOAD_N_REG and TIMER0_ON_REG. Upon reset, the counter and register values are 0x0000. Timer 0 will generate a Pulse Width Modulated signal PWM0. The frequency and duty cycle of PWM0 are determined by the contents of the TIMER0_RELOAD_N_REG and the TIMER0_RELOAD_M_REG registers.
ISM14585-L35 Specification Timer 0 PWM Mode If bit TIM0_CTRL in the TIMER0_CTRL_REG is set, Timer 0 will start running. SWTIM_IRQ will be generated and the T0-counter will load its start value from the TIMER0_RELOAD_M_REG register, and will decrement on each clock. The ONcounter also loads its start value from the TIMER0_ON_REG register and decrements with the selected clock.
ISM14585-L35 Specification Figure 34 Timer 0 PWM Mode At start-up both counters and the PWM0 signal are LOW so also at start-up an interrupt is generated. If Timer 0 is disabled all flip-flops, counters and outputs are in reset state except for the ON-register, the TIMER0_RELOAD_N_REG register and the TIMER0_RELOAD_M_REG register. The timer input registers ON-register, TIMER0_RELOAD_N_REGand TIMER0_RELOAD_M_REG can be written, and the counter registers ON-counter and T0-counter can be read.
ISM14585-L35 Specification • Input clock frequency: MHz or 32 kHz • Programmable output frequency: • Three outputs with programmable duty cycle from 0% to 100% • Used for white LED intensity (on/off) control with N = 1, 2, 4 or 8 and sys_clk = 16 Figure 35 Timer 2 PWM Block Diagram DOC-DS-14585-201807-3.
ISM14585-L35 Specification The Timer 2 is clocked with the system clock divided by TMR_DIV (1, 2, 4 or 8) and can be enabled with TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE]. T2_FREQ_CNTR determines the output frequency of the T2_PMWn output. This counter counts down from the value stored in register TRIPLE_PWM_FREQUENCY. At counter value 0, T2_FREQ_CNTR sets the T2_PWMn output to ‘1’ and the counter is reloaded again. T2_DUTY_CNTR is an up-counter that determines the duty cycle of the T2_PWMn output signal.
ISM14585-L35 Specification Figure 36 Timer 2 PWM Timing Diagram 9.12 Watchdog Timer The Watchdog Timer is an 8-bit timer with sign bit that can be used to detect an unexpected execution sequence caused by a software run-away and can generate a full system reset or a Non- Maskable Interrupt (NMI). Features: • 8 bits down counter with sign bit, clocked with a 10.24ms clock for a maximum 2.6s time-out. • Non-Maskable Interrupt (NMI) or WDOG reset.
ISM14585-L35 Specification Figure 37 Watchdog Timer Block Diagram The 8 bits watchdog timer is decremented by 1 every 10.24ms. The timer value can be accessed through the WATCHDOG_REG register which is set to 255 (FF16) at reset. This results in a maximum watchdog time-out of ~2.6s. During write access the WATCHDOG_REG[WDOG_WEN] bits must be 0. This provides extra filtering for a software run-away writing all ones to the WATCHDOG_REG.
ISM14585-L35 Specification 9.13 Input/Output Ports The ISM14585-L35 has software-configurable I/O pin assignment, organized into ports Port 0, Port 1. . Features: • • • • • • Port 0: 8 pins, Port 1: 4 pins Fully programmable pin assignment Selectable 25kΩ pull-up, pull-down resistors per pin Pull-up voltage is VBAT3V (BUCK mode) Fixed assignment for analog pin ADC[3:0] Pins can retain their last state when system enters the Extended or Deep Sleep mode.
ISM14585-L35 Specification 9.13.1 PROGRAMMABLE PIN ASSIGNMENT The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/O pins of on-chip peripherals. Any peripheral input or output signal can be freely mapped to any I/O port bit by setting Pxy_MODE_REG[4-0]: 0x00 to 0x1F: Peripheral IO ID (PID) Refer to the Px_MODE_REGs for an overview of the available PIDs. Analog ADC has fixed pin assignment in order to limit interference with the digital domain.
ISM14585-L35 Specification 9.13.2.1 PORT DATA REGISTER The registers input Px_DATA_REG and output Px_DATA_REG are mapped on the same address. The data input register (Px_DATA_REG) is a read-only register that returns the current state on each port pin even if the output direction is selected, regardless of the programmed PID, unless the analog function is selected (in this case it reads 0). The ARM CPU can read this register at any time even when the pin is configured as an output.
ISM14585-L35 Specification 9.14 General Purpose ADC The ISM14585-L35 is equipped with a high-speed ultra-low power 10-bit general purpose Analog-to-Digital Converter (GPADC). It can operate in unipolar (single ended) mode as well as in bipolar (differential) mode. The ADC has its own voltage regulator (LDO) of 1.2 V, which represents the full scale reference voltage. Features: • • • • • • • • • 10-bit dynamic ADC with 65 ns conversion time Maximum sampling rate 3.
ISM14585-L35 Specification 9.14.1 INPUT CHANNELS AND INPUT SCALE The ISM14585-L35 has a multiplexer between the ADC and four specific GPIO ports (P0_0 to P0_3). Furthermore, the ADC can also be used to monitor the battery voltage and several internal voltages of the system (see GP_ADC_CTRL_REG). Single-ended or differential operation is selected via bit GP_ADC_CTRL_REG[GP_ADC_SE]. In differential mode the voltage difference between two GPIO input ports will be converted.
ISM14585-L35 Specification 9.14.3 NON-IDEAL EFFECTS Besides Differential Non-Linearity (DNL) and Integral Non-Linearity (INL), each ADC has a gain error (linear) and an offset error (linear). The gain error of the GPADC slightly reduces the effective input scale (up to 50 mV). The offset error causes the effective input scale to become non-centered. The offset error of the GPADC is less than 20 mV and can be reduced by chopping or by offset calibration. The ADC result will also include some noise.
ISM14585-L35 Specification With bit GP_ADC_CTRL_REG[GP_ADC_MUTE], the ADC input is switched to the center scale input level, so the ADC result ideally is 511.5. If instead a value of 515 is observed, the output offset is +3.5 (adc_off_p = 3.5). With bit GP_ADC_CTRL_REG[GP_ADC_SIGN] the sign of the ADC input and output is changed. Two sign changes have no effect on the signal path, though the sign of the ADC offset will change. If adc_off_p = 3.5 the ADC_result with opposite GP_ADC_SIGN will be 508.
ISM14585-L35 Specification 9.14.6 ZERO-SCALE ADJUSTMENT The GP_ADC_OFFP and GP_ADC_OFFN registers can also be used to set the zeroscale or full-scale input level at a certain target value. For instance, they can be used to calibrate GP_ADC_RESULT to 0x000 at an input voltage of exactly 0.0 V, or to calibrate the zero scale of a sensor. 9.14.7 COMMON MODE ADJUSTMENT The common mode level of the differential signal must be 0.6 V (or 1.8 V with GP_ADC_ATTN3X = 1). If the common mode input level of 0.
ISM14585-L35 Specification sampling capacitor. The conversion time is approximately one clock cycle of 16 MHz (62.5 ns). 7 * ROUT * 0.2 pF - 62.5 ns < 1/fS => ROUT < (1 + 62.5 ns * fS) / (7 * 0.2 pF * fS) Examples: ROUT < 7.2 MΩ at fS = 100 kHz ROUT < 760 kΩ at fS = 1 MHz The inductance from the signal source to the ADC input pin must be very small. Otherwise, filter capacitors are required from the input pins to ground (differential mode: from pin to pin).
ISM14585-L35 Specification GP_ADC_DELAY_EN in register GP_ADC_CTRL2_REG. The delay counter starts counting when the GP_ADC_START bit is programmed while the GP_ADC_DELAY_EN bit is set. The counter is stopped after the conversion is finished. The delay counter must be reset before reuse, which is typically only required after the LDO was disabled. Bit GP_ADC_DELAY_EN must be made zero to reset the counter. It is recommended to check that this bit is zero before (re)activating it. 9.14.
ISM14585-L35 Specification 9.14.11 SRC ARCHITECTURE 9.14.11.1 I/O CHANNELS The SRC block converts two 24 bits channels either as a stereo pair or as two mono channels. The PCM linear data pairs are received on SRC_IN and the output is 2x24 bits left aligned on SRC_OUT. The two 1 bit PDM data inputs are received on PDM_IN and are converted to 2x24 bits, left aligned to SRC_OUT. 9.14.11.2 I/O MULTIPLEXERS The SRCx_IN input multiplexer (Figure 40) is controlled by APU_MUX_REG.
ISM14585-L35 Specification 9.14.11.5 DMA OPERATION If more than one sample must be transfer to/from the CPU or the sample rate is so high that it interrupts the CPU too often, the DMA controller must be engaged to perform the transactions. 9.14.11.6 INTERRUPTS After a Sample Rate Conversion, the input up-sampler and output down-sampler generate edge triggered interrupts on SRC_IN_SYNC and SRC_OUT_SYNC to the CPU which do not have to be cleared.
ISM14585-L35 Specification 9.15 PDM Interface The Pulse Density Modulation (PDM) interface provides a serial connection for up-to 2 input devices (e.g MEMS microphones) or output devices. The interfaces have a common clock PDM_CLK and one input PDM_DI which is capable of carrying two channels. Figure 41 shows a typical connection of two microphones sharing one data line.
ISM14585-L35 Specification Figure 42 PDM formats Figure 43 PDM input transfer functions It should be noted that the audio quality degrades when the oversampling ratio is less than 64. For an 8 kHz sample rate the minimum recommended PDM clock rate is 64 x 8 kHz = 512 kHz. DOC-DS-14585-201807-3.
ISM14585-L35 Specification 9.16 PCM Controller The PCM controller is implementing an up-to 192kHz synchronous interface to external audio devices, ISDN circuits and serial data interfaces. It is accessed through the APB32 interface. PCM can individually operate in master or slave mode. In slave mode, the phase between the external and internal frame sync can be measured and used to compensate for drift. The data IO registers have DMA support in order to reduce the interrupt overhead to the CPU.
ISM14585-L35 Specification Figure 44 PCM controller 9.16.1 PCM ARCHITECTURE 9.16.1.1 • • • • INTERFACE SIGNALS PCM_FSC, strobe signal input, output. Supports 8/16/32/48/96/128/192kHz. Can generate an interrupt to the CPU. PCM_CLK, PCM clock input, output. PCM_DO, PCM Data output, push pull or open drain with external pull-up resistor. PCM_DI, PCM Data input. PCM interface can be powered down by the PCM1_CTRL_REG[PCM_EN] = 0. 9.16.1.
ISM14585-L35 Specification 9.16.1.3 CHANNEL DELAY The 8 PCM channels can be delayed with a maximum delay of 31x8bits using the bit field PCM1_CTRL_REG[PCM_CH_DEL]. Note that a high delay count in combination with a slow clock, can lead to the PCM_FSC sync occurring before all channels are shifted in or out. The received bits of the current channel may not be properly aligned in that case. 9.16.1.
ISM14585-L35 Specification The PCM_DIV_REG calculations show the following use cases, with 8 bits, 16 bits, 32 bits and 48 bits.
ISM14585-L35 Specification 9.16.1.5 DATA FORMATS 9.16.1.5.1 PCM MASTER MODE Master mode is selected if PCM1_CTRL_REG[PCM_MASTER] = 1. In master mode PCM_FSC is output and falls always over Channel 0. The duration of PCM_FSC is programmable with PCM1_CTRL_REG[PCM_FSCLEN]= 1 or 8,16, 24, 32 clock pulses high. The start position is programmable with PCM1_CTRL_REG[PCM_FSCDEL] and can be placed before or on the first bit of channel 0.
ISM14585-L35 Specification Figure 46 PCM interface formats 9.16.1.5.3 I2S FORMATS The digital audio interface supports I2S mode, Left Justified mode, Right Justified mode and TDM mode. I2S mode To support I2S mode, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the PCM_FSC, and the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the PCM_FSC. DOC-DS-14585-201807-3.
ISM14585-L35 Specification Settings for I2S mode: • PCM_FSC_EDGE: 1 (all after PCM_FSC) • PCM_FSCLEN: 4 (4x8 High, 4x8 Low) • PCM_FSC_DEL: 0 (one bit delayed) • PCM_CLK_INV: 1 (output on falling edge) • PCM_CH0_DEL: 0 (no channel delay) Figure 47 I2S Mode TDM mode A time is specified from the normal ‘start of frame’ condition using register bits PCM_CH_DEL.
ISM14585-L35 Specification Figure 48 I2S TDM mode (left justified mode) 9.16.1.5.4 IOM MODE In the IOM format, the PCM_CLK frequency is twice the data bit cell duration. In slave mode synchronization is on the first rising edge of PCM_FSC while data is clock in on the second falling edge.
ISM14585-L35 Specification 9.16.1.6 EXTERNAL SYNCHRONIZATION With the PCM interface in slave mode, the PCM interface supports direct routing through the sample rate converter (SRC). Any drift in PCM_FSC or other frame sync frequencies like 44.1 kHz can be directly resampled to e.g 48kHz internal sample rate. 10 MECHANICAL SPECIFICATION 10.1 Size of the Module The following paragraphs provide the requirements for the size and weight. The size and thickness of the ISM14585-L35 SiP is: • • 6mm (W) x 8.
ISM14585-L35 Specification 11 Recommend Footprint (Board Design) 11.1 Module Dimension Measurement Unit: mm TOP View Note: • Please use Un-Solder Mask to design the Module Footprint. • There are two types pad size in the Module. o Rectangle : Pad size: 0.3 x 0.5 mm & Solder Mask size: 0.375 x 0.575 mm o Circle: Pad size (Φ): 0.5 mm & Solder Mask size (Φ): 0.6 mm • Please contact Inventek Systems for interest in a chip-down design. DOC-DS-14585-201807-3.
ISM14585-L35 Specification 11.2 The X-Y Central Location Coordinates Unit: mm (Drawn dimensions with chip 0,0 at bottom right corner) (0,0) PIN_NUMBER PAD_Size (mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 x x x x x x x x x x x x x x 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Solder Mask_Size (mm) 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 0.575 x x x x x x x x x x x x x x 0.375 0.375 0.375 0.375 0.
ISM14585-L35 Specification PIN_NUMBER PAD_Size (mm) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 x 0.3 0.5 mm (Φ) Solder Mask_Size (mm) 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.575 x 0.375 0.
ISM14585-L35 Specification 12 Recommend Stencil Unit: mm TOP View Recommend: 1. ≦ 0.08mm THK stencil will has better solder paste deposit. 2. Type 4 or 5 solder ( fine powder size) will has better solution no matter clean or nonclean solder paste. 3. Nitrogen reflow oven. DOC-DS-14585-201807-3.
ISM14585-L35 Specification 13 Recommended Reflow Profile Temperature 2450c 2170c 2000c 1500c Time Pre-heating Soldering 90~120 sec 60~90 sec 14 Storage Requirements 14.1 MSD Specification DOC-DS-14585-201807-3.
ISM14585-L35 Specification 15 REVISION CONTROL Document: ISM14585-L35 External Release 5.0 BLE + Cortex M0 Module DOC-DS-14585-201807-3.0 Date 7/04/2018 Author AS Revision 1.0 Comment Preliminary 7/04/2019 AS 2.0 10/9/19 10/10/2019 10/23/19 AS AS AS 2.5 3.0 3.1 Schematics, Antenna Options and Buck Power Update MSD Specification w.
