Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 17
Pin Name
Pin
Number
I/O Type
Description
Digital I/O
P0_0 (Note2)
18
DIO / ADC 0 /
SPI CLK
INPUT/OUTPUT with selectable pull up/down resistor. Pulldown
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
Drive current is 3.5mA
Note 1: An increased Packet Error rate might occur if GPIO P1-2
and P1-3 is toggling. The root cause of this problem is the
close location of a few GPIO pins to the on-chip 16 MHz
XTAL oscillator circuitry. Toggling of these GPIOs might
corrupt the clock, which will be visible in the Packet Error
Rate.
Note 2: All Port Pins can be PWM
Note 3: There is no execute in place from the SPI Flash, therefore
UART is available after Boot or the UART can be
interleaved with SPI. If configured, the SPI Flash can be
used to load FW.
P0_1 (Note2)
29
DIO / ADC 1
P0_2 (Note2)
30
DIO / ADC 2 /
I2C SCL
P0_3 (Note2)
17
DIO / ADC 3 /
I2C SDA
P0_4 (Note2)
23
DIO / UART
TX
P0_5 (Note2 & 3)
21
DIO / UART
RX / SPI
MISO
P0_6 (Note2)
20
DIO / SPI
MOSI
P1_2 (Note 1 & 2)
13
DIO
P1_3 (Note 1 & 2)
14
DIO
Debug Interface
SWCLK
2
DIO
This signal is the JTAG clock by default
SWDIO
3
DIO
This signal is the JTAG data I/O by default
No Connects
NC
4,5,16, 22,27
NA
RESERVED