Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 18
9 Addition Information
9.1 Microcontroller Unit
The ISM14585-L35 includes a Cortex-M0 32-bit Reduced Instruction Set Computing
(RISC) processor with a von Neumann architecture (single bus interface). It uses an
instruction set called Thumb, which was first supported in the ARM7TDMI processor.
However, several newer instructions from the ARMv6 architecture and a few
instructions from the Thumb-2 technology are also included. Thumb-2 technology
extends the previous Thumb instruction set to allow all operations to be carried out in
one CPU state. The instruction set in Thumb-2 includes both 16-bit and 32-bit
instructions. Most instructions generated by the C compiler use the 16-bit instructions,
and the 32-bit instructions are used when the 16-bit version cannot carry out the
required operations. This results in high code density and avoids the overhead of
switching between two instruction sets.
In total, the Cortex-M0 processor supports 56 base instructions, although some
instructions can have more than one form. Although the instruction set is small, the
Cortex-M0 processor is highly capable because the Thumb instruction set is highly
optimized.
Academically, the Cortex-M0 processor is classified as load-store architecture, as it has
separate instructions for reading and writing to memory, and instructions for arithmetic
or logical operations that use registers.