Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 21
1. The PWR-On reset which is triggered by a GPIO set as POR source with
selectable polarity and/or the RST pad after a programmable time delay.
2. The HW reset which is basically triggered by the RST pad when it becomes
active for a short period of time (less than the programmable delay for POR).
3. The SW reset which is triggered by writing the SYS_CTRL_REG[SW_RESET]
bit.
• The HW reset can also be automatically activated upon waking up of the system
from the Extended or Deep Sleep mode by programming bit PMU_CTRL_REG
[RESET_ON_WAKEUP].
• The PWR-On reset as well as the HW reset will basically run the cold start-up
sequence and the BootROM code will be executed.
The SW reset is the logical OR of a signal from the ARM CPU (triggered by writing
SCB->AIRCR = 0x05FA0004) and the SYS_CTRL_REG[SW_RESET] bit.
This is mainly used to reboot the system after the base address has been remapped.
The block diagram of the reset block is depicted in Figure 5.
Figure 5. Reset Block Diagram
Certain registers are reset by POR only or by POR and the HW reset signal, but not by
the SW reset. These registers are listed in the table below.