Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 3
9.5.3 DMA CHANNEL OPERATION ............................................................................. 26
9.5.4 DMA ARBITRATION ............................................................................................. 27
9.5.5 FREEZING DMA CHANNELS............................................................................... 28
9.6 I2C Interface ................................................................................................................. 28
9.7 I2C BUS TERMS ......................................................................................................... 30
9.7.2 I2C BEHAVIOR ....................................................................................................... 32
9.7.3 I2C PROTOCOLS .................................................................................................... 34
9.7.4 MULTIPLE MASTER ARBITRATION ................................................................. 39
9.7.5 CLOCK SYNCHRONIZATION .............................................................................. 41
9.7.6 OPERATION MODES ............................................................................................. 41
9.7.7 DISABLING THE I2C CONTROLLER .................................................................. 47
9.8 UART ............................................................................................................................ 48
9.8.1 UART (RS232) SERIAL PROTOCOL .................................................................... 49
9.8.2 IRDA 1.0 SIR PROTOCOL ..................................................................................... 50
9.8.3 CLOCK SUPPORT .................................................................................................. 52
9.8.4 CLOCK SUPPORT .................................................................................................. 52
9.8.5 PROGRAMMABLE THRE INTERRUPT .............................................................. 53
9.8.6 SHADOW REGISTERS ........................................................................................... 55
9.8.7 DIRECT TEST MODE ............................................................................................. 56
9.9 SPI+ Interface ............................................................................................................... 56
9.9.1 OPERATION WITHOUT FIFOS ............................................................................ 57
9.10 Wake-Up Timer ............................................................................................................ 62
9.11 General Purpose Timers ................................................................................................ 63
9.11.1 TIMER 0 ............................................................................................................... 64
9.11.2 TIMER 2 ............................................................................................................... 67
9.12 Watchdog Timer ........................................................................................................... 70
9.13 Input/Output Ports ......................................................................................................... 72
9.13.1 PROGRAMMABLE PIN ASSIGNMENT .......................................................... 73
9.13.2 GENERAL PURPOSE PORT REGISTERS ........................................................ 73
9.14 General Purpose ADC................................................................................................... 75
9.14.1 INPUT CHANNELS AND INPUT SCALE ........................................................ 76
9.14.2 STARTING THE ADC AND SAMPLING RATE .............................................. 76
9.14.3 NON-IDEAL EFFECTS ....................................................................................... 77
9.14.4 CHOPPING........................................................................................................... 77
9.14.5 OFFSET CALIBRATION .................................................................................... 78
9.14.6 ZERO-SCALE ADJUSTMENT ........................................................................... 79
9.14.7 COMMON MODE ADJUSTMENT .................................................................... 79
9.14.8 INPUT IMPEDANCE, INDUCTANCE, AND INPUT SETTLING ................... 79
9.14.9 COMMON MODE ADJUSTMENT .................................................................... 80
9.14.10 Sample Rate Converter (SRC) .............................................................................. 81
9.14.11 SRC ARCHITECTURE........................................................................................ 82
9.15 PDM Interface ............................................................................................................... 84
9.16 PCM Controller ............................................................................................................. 86
9.16.1 PCM ARCHITECTURE ....................................................................................... 87