Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 27
Figure 8 DMA Channel Diagram
If at the end of a DMA cycle, the DMA start condition is still true, the DMA continues.
The DMA stops if DREQ_MODE is low or if DMAx_LEN_REG is equal to the internal
index register. This condition also clears the DMA_ON bit.
If bit CIRCULAR is set to 1, the DMA controller automatically resets the internal index
registers and continues from its starting address without intervention of the ARM
CortexTM M0. If the DMA controller is started with DREQ_MODE =0, the DMA will
always stop, regardless of the state of CIRCULAR.
Each DMA channel can generate an interrupt if DMAx_INT_REG if equal to
DMAx_IDX_REG. After the transfer and before DMAx_IDX_REG is incremented, the
interrupt is generated. Example: if DMA_x_INT_REG=0 and DMA_x_LEN_REG=0,
there will be one transfer and an interrupt.
9.5.4 DMA ARBITRATION
The priority level of a DMA channel can be set with bits DMA_PRIO[2-0]. These bits
determine which DMA channel will be activated in case more than one DMA channel