Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 29
• Two-wire I2C serial interface consists of a serial data line (SDA) and a serial
clock (SCL)
• Two speeds are supported:
o Standard mode (0 to 100kbit/s)
o Fast mode (<= 400kbit/s)
• Clock synchronization
• 32B deep transmit/receive FIFOs
• Master transmit, Master receive operation
• 7-bit or 10-bit addressing
• 7-bit or 10-bit combined format transfers
• Bulk transmit mode
• Default slave address of 0x055
• Interrupt or polled-mode operation
• Handles Bit and Byte waiting at both bus speeds
• Programmable SDA hold time
• DMA support
Figure 9 I2C Controller Block Diagram
The I2C Controller block diagram shown in Figure 9 contains the following sub-blocks:
• AMBA Bus Interface Unit: Interfacing via the APB interface to access the register
file.
• Register File: Contains configuration registers and is the interface with software.
• Master State Machine: Generates the I2C protocol for the master transfers.
• Clock Generator: Calculates the required timing to do the following:
o Generate the SCL clock when configured as a master