Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 30
o Check for bus idle
o Generate a START and a STOP
o Setup the data and hold the data
• Rx Shift: Takes data into the design and extracts it in byte format.
• Tx Shift: Presents data supplied by CPU for transfer on the I2C bus.
• Rx Filter: Detects the events in the bus; for example, start, stop and arbitration
lost.
• Toggle: Generates pulses on both sides and toggles to transfer signals across
clock domains.
• Synchronizer: Transfers signals from one clock domain to another.
• Interrupt Controller: Generates the raw interrupt and interrupt flags, allowing
them to be set and cleared.
• RX FIFO/TX: Holds the RX FIFO and TX FIFO register banks and controllers,
along with their status levels.
9.7 I2C BUS TERMS
• The following terms relate to how the role of the I2C device and how it interacts
with other I2C devices on the bus.
• Transmitter. The device that sends data to the bus. A transmitter can either be a
device that initiates the data transmission to the bus (a master-transmitter) or
responds to a request from the master to send data to the bus (a slave-
transmitter).
• Receiver. The device that receives data from the bus. A receiver can either be a
device that receives data on its own request (a master-receiver) or in response to
a request from the master (a slave-receiver).
• Master. The component that initializes a transfer (START command), generates
the clock (SCL) signal and terminates the transfer (STOP command). A master
can be either a transmitter or a receiver.
• Slave. The device addressed by the master. A slave can be either receiver or
transmitter. These concepts are illustrated in Figure 10.