Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 33
master then acknowledges the transaction with the ACK pulse. This transaction
continues until the master terminates the transmission by not acknowledging (NACK)
the transaction after the last byte is received, and then the master issues a STOP
condition or addresses another slave after issuing a RESTART condition. This behavior
is illustrated in Figure 11.
Figure 11 Data Transfer on the I2C Bus
The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and
changes only while the SCL line is low, except for STOP, START, and RESTART
conditions. The output drivers are open-drain or open-collector to perform wire-AND
functions on the bus. The maximum number of devices on the bus is limited by only the
maximum capacitance specification of 400pF. Data is transmitted in byte packages.
9.7.2.1 START AND STOP GENERATION
When operating as an I2C master, putting data into the transmit FIFO causes the I2C
Controller to generate a START condition on the I2C bus. Allowing the transmit FIFO to
empty causes the I2C Controller to generate a STOP condition on the I2C bus.
When operating as a slave, the I2C Controller does not generate START and STOP
conditions, as per the protocol. However, if a read request is made to the I2C Controller,
it holds the SCL line low until read data has been supplied to it. This stalls the I2C bus
until read data is provided to the slave I2C Controller, or the I2C Controller slave is
disabled by writing a 0 to I2C_ENABLE.