Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 34
9.7.2.2 COMBINED FORMATS
The I2C Controller supports mixed read and write combined format transactions in both
7-bit and 10-bit addressing modes.
The I2C Controller does not support mixed address and mixed address format - that is,
a 7-bit address transaction followed by a 10-bit address transaction or vice versa -
combined format transactions.
To initiate combined format transfers, I2C_CON.I2C_RESTART_EN should be set to 1.
With this value set and operating as a master, when the I2C Controller completes an
I2C transfer, it checks the transmit FIFO and executes the next transfer. If the direction
of this transfer differs from the previous transfer, the combined format is used to issue
the transfer. If the transmit FIFO is empty when the current I2C transfer completes, a
STOP is issued, and the next transfer is issued following a START condition.
9.7.3 I2C PROTOCOLS
The I2C Controller has the following protocols:
• START and STOP Conditions
• Addressing Slave Protocol
• Transmitting and Receiving Protocol
• START BYTE Transfer Protocol
9.7.3.1 START AND STOP CONDITIONS
When the bus is idle, both the SCL and SDA signals are pulled high through external
pull-up resistors on the bus. When the master wants to start a transmission on the bus,
the master issues a START condition. This is defined to be a high-to-low transition of
the SDA signal while SCL is 1. When the master wants to terminate the transmission,
the master issues a STOP condition. This is defined to be a low-to-high transition of the
SDA line while SCL is 1. Figure 12 shows the timing of the START and STOP
conditions. When data is being transmitted on the bus, the SDA line must be stable
when SCL is 1.