Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 35
Figure 12 START and STOP Conditions
Note: The signal transitions for the START/STOP conditions, as depicted in Figure 12,
reflect those observed at the output signals of the Master driving the I2C bus. Care
should be taken when observing the SDA/SCL signals at the input signals of the
Slave(s), because unequal line delays may result in an incorrect SDA/SCL timing
relationship.
9.7.3.2 ADDRESSING SLAVE PROTOCOL
There are two address formats: 7-bit address format and 10-bit address format.
7-bit Address Format
During the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the
slave address and the LSB bit (bit 0) is the R/W bit as shown in Figure 13. When bit 0
(R/W) is set to 0, the master writes to the slave. When bit 0 (R/W) is set to 1, the master
reads from the slave.
Figure 13 7-bit Address Format