Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 40
For high-speed mode, the arbitration cannot go into the data phase because each
master is programmed with a unique high-speed master code. This 8-bit code is defined
by the system designer and is set by writing to the High Speed Master Mode Code
Address Register, I2C_HS_MADDR. Because the codes are unique, only one master
can win arbitration, which occurs by the end of the transmission of the high-speed
master code.
Control of the bus is determined by address or master code and data sent by competing
masters, so there is no central master or any order of priority on the bus. Arbitration is
not allowed between the following conditions:
• A RESTART condition and a data bit
• A STOP condition and a data bit
• A RESTART condition and a STOP condition
Slaves are not involved in the arbitration process.
Figure 18 Multiple Master Arbitration