Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 41
9.7.5 CLOCK SYNCHRONIZATION
When two or more masters try to transfer information on the bus at the same time, they
must arbitrate and synchronize the SCL clock. All masters generate their own clock to
transfer messages. Data is valid only during the high period of SCL clock. Clock
synchronization is performed using the wired-AND connection to the SCL signal. When
the master transitions the SCL clock to 0, the master starts counting the low time of the
SCL clock and transitions the SCL clock signal to 1 at the beginning of the next clock
period. However, if another master is holding the SCL line to 0, then the master goes
into a HIGH wait state until the SCL clock line transitions to 1.
All masters then count off their high time and the master with the shortest high time
transitions the SCL line to 0. The masters then counts out their low time and the one
with the longest low time forces the other master into a HIGH wait state. Therefore, a
synchronized SCL clock is generated, which is illustrated in Figure 19. Optionally,
slaves may hold the SCL line low to slow down the timing on the I2C bus.
Figure 19 Multiple Master Clock Synchronization
9.7.6 OPERATION MODES
This section provides information on the following topics:
• Slave mode operation
• Master mode operation
Note: It is important that the I2C Controller should only be set to operate as an I2C
Master, or I2C Slave, but not both simultaneously. This is achieved by ensuring that bit
6 (I2C_SLAVE_DISABLE) and bit 0 (I2C_MASTER_MODE) of the I2C_CON register
are never set to 0 and 1, respectively.