Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 43
3. The I2C Controller asserts the RD_REQ interrupt (bit 5 of the
I2C_RAW_INTR_STAT register) and holds the SCL line low. It is in a wait state
until software responds. If the RD_REQ interrupt has been masked, due to
I2C_INTR_MASK[5] register (M_RD_REQ bit field) being set to 0, then it is
recommended that a hardware and/or software timing routine be used to instruct
the CPU to perform periodic reads of the I2C_RAW_INTR_STAT register.
a. Reads that indicate I2C_RAW_INTR_STAT[5] (R_RD_REQ bit field) being
set to 1 must be treated as the equivalent of the RD_REQ interrupt being
asserted.
b. Software must then act to satisfy the I2C transfer.
c. The timing interval used should be in the order of 10 times the fastest SCL
clock period the I2C Controller can handle. For example, for 400 kb/s, the
timing interval is 25us.
i. Note: The value of 10 is recommended here because this is
approximately the amount of time required for a single byte of data
transferred on the I2C bus.
4. If there is any data remaining in the TX FIFO before receiving the read request,
then the I2C Controller asserts a TX_ABRT interrupt (bit 6 of the
I2C_RAW_INTR_STAT register) to flush the old data from the TX FIFO.
a. Note: Because the I2C Controller’s TX FIFO is forced into a flushed/reset
state whenever a TX_ABRT event occurs, it is necessary for software to
release the I2C Controller from this state by reading the
I2C_CLR_TX_ABRT register before attempting to write into the TX FIFO.
See register I2C_RAW_INTR_STAT for more details.
5. If the TX_ABRT interrupt has been masked, due to of I2C_INTR_MASK[6]
register (M_TX_ABRT bit field) being set to 0, then it is recommended that re-
using the timing routine (described in the previous step), or a similar one, be
used to read the I2C_RAW_INTR_STAT register.
a. Reads that indicate bit 6 (R_TX_ABRT) being set to 1 must be treated as
the equivalent of the TX_ABRT interrupt being asserted.
b. There is no further action required from software.
c. The timing interval used should be similar to that described in the previous
step for the I2C_RAW_INTR_STAT[5] register.
6. Software writes to the I2C_DATA_CMD register with the data to be written (by
writing a ‘0’ in bit 8).
7. Software must clear the RD_REQ and TX_ABRT interrupts (bits 5 and 6,
respectively) of the I2C_RAW_INTR_STAT register before proceeding.