Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 44
8. If the RD_REQ and/or TX_ABRT interrupts have been masked, then clearing of
the I2C_RAW_INTR_STAT register will have already been performed when
either the R_RD_REQ or R_TX_ABRT bit has been read as 1.
9. The I2C Controller releases the SCL and transmits the byte.
10. The master may hold the I2C bus by issuing a RESTART condition or release the
bus by issuing a STOP condition.
Slave-Receiver Operation for a Single Byte
When another I2C master device on the bus addresses the I2C Controller and is
sending data, the I2C Controller acts as a slave-receiver and the following steps occur:
1. The other I2C master device initiates an I2C transfer with an address that matches the
I2C Controller’s slave address in the I2C_SAR register.
2. The I2C Controller acknowledges the sent address and recognizes the direction of the
transfer to indicate that the I2C Controller is acting as a slave-receiver.
3. I2C Controller receives the transmitted byte and places it in the receive buffer.
4. If the RX FIFO is completely filled with data when a byte is pushed, then an overflow
occurs, and the I2C Controller continues with subsequent I2C transfers. Because a
NACK is not generated, software must recognize the overflow when indicated by the I2C
Controller (by the R_RX_OVER bit in the I2C_INTR_STAT register) and take
appropriate actions to recover from lost data. Hence, there is a real time constraint on
software to service the RX FIFO before the latter overflow as there is no way to re-apply
pressure to the remote transmitting master. You must select a deep enough RX FIFO
depth to satisfy the interrupt service interval of their system.
5. I2C Controller asserts the RX_FULL interrupt (I2C_RAW_INTR_STAT[2] register).
6. If the RX_FULL interrupt has been masked, due to setting I2C_INTR_MASK[2] register
to 0 or setting I2C_TX_TL to a value larger than 0, then it is recommended that a timing
routine (described in “Slave-Transmitter Operation for a Single Byte”) be implemented
for periodic reads of the I2C_STATUS register. Reads of the I2C_STATUS register, with
bit 3 (RFNE) set at 1, must then be treated by software as the equivalent of the
RX_FULL interrupt being asserted.
7. Software may read the byte from the I2C_DATA_CMD register (bits 7:0).
8. The other master device may hold the I2C bus by issuing a RESTART condition or
release the bus by issuing a STOP condition.
Slave-Transfer Operation for Bulk Transfers
In the standard I2C protocol, all transactions are single byte transactions and the
programmer responds to a remote master read request by writing one byte into the
slave’s TX FIFO. When a slave (slave-transmitter) is issued with a read request