Data Sheet

ISM14585-L35 Specification

DOC-DS-14585-201807-3.0

Confidential Inventek Systems

Page 46

transferred to the processor bus clock domain where the FIFO exists and the contents

of the TX FIFO is cleared at that time.

9.7.6.2 MASTER MODE OPERATION

This section includes the following topics:

• Initial Configuration

• Master Transmit and Master Receive

Initial Configuration

The procedures are very similar and are only different with regard to where the

I2C_10BITADDR_MASTER bit is set (either bit 4 of I2C_CON register or bit 12 of

I2C_TAR register).

To use the I2C Controller as a master perform the following steps:

1. Disable the I2C Controller by writing 0 to the I2C_ENABLE register.

2. Write to the I2C_CON register to set the maximum speed mode supported (bits

2:1) and the desired speed of the I2C Controller master-initiated transfers, either

7-bit or 10-bit addressing (bit 4).

3. Ensure that bit 6 I2C_SLAVE_DISABLE = 1 and bit 0 MASTER_MODE =1

a. Note: Slaves and masters do not have to be programmed with the same

type of addressing 7-bit or 10-bit address. For instance, a slave can be

programmed with 7-bit addressing and a master with 10-bit addressing,

and vice versa.

4. Write to the I2C_TAR register the address of the I2C device to be addressed

(bits 9:0). This register also indicates whether a General Call or a START BYTE

command is going to be performed by I2C.

5. Only applicable for high-speed mode transfers. Write to the I2C_HS_MADDR

programmer-defined.