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ManualsBrandsInventek Systems ManualsElectronicsBLE 5.0 Radio Module for Portable or Mobile config
51525354555657585960
ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 48
1. Define a timer interval (ti2c_poll) equal to the 10 times the signaling period for the
highest I2C transfer speed used in the system and supported by I2C Controller. For
example, if the highest I2C transfer mode is 400kbit/s, then this ti2c_poll is 25 μs.
2. Define a maximum time-out parameter, MAX_T_POLL_COUNT, such that if any
repeated polling operation exceeds this maximum value, an error is reported.
3. Execute a blocking thread/process/function that prevents any further I2C master
transactions to be started by software but allows any pending transfers to be completed.
a. Note: This step can be ignored if I2C Controller is programmed to operate as an
I2C slave only.
4. The variable POLL_COUNT is initialized to zero.
5. Set I2C_ENABLE to 0.
6. Read the I2C_ENABLE_STATUS register and test the I2C_EN bit (bit 0). Increment
POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the
relevant error code.
7. If I2C_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the previous
step.
Otherwise, exit with a relevant success code.
9.8 UART
The ISM14585-L35 contains two identical instances of this block, i.e. UART and
UART2. The UART is compliant to the industry-standard 16550 and is used for serial
communication with a peripheral. Data is written from a master (CPU) over the APB bus
to the UART and it is converted to serial form and transmitted to the destination device.
Serial data is also received by the UART and stored for the master (CPU) to read back.
There is also DMA support on the UART block thus the internal FIFOs can be used.
Both UARTs support hardware flow control signals (RTS, CTS).
Features:
• 16 bytes Transmit and receive FIFOs
• Hardware flow control support (CTS/RTS)
• Shadow registers to reduce software overhead and also include a software
programmable reset
• Transmitter Holding Register Empty (THRE) interrupt mode
• IrDA 1.0 SIR mode supporting low power mode.
• Functionality based on the 16550 industry standard:
• Programmable character properties, such as number of data bits per character
(5-8), optional parity bit (with odd or even select) and number of stop bits (1, 1.5
or 2)