Data Sheet
ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 52
It should be noted that for all sclk frequencies greater than or equal to 7.37MHz (and
obey the requirements of the Low Power Divisor Latch registers), pulses of 1.41μs are
detectable. However, there are several values of sclk that do not allow the detection of
such a narrow pulse and these are as follows:
Table: Low Power Divisor Latch Register Values:
SCLK
Low Power Divisor Latch Register Value
Min Pulse Width for Detection
1.84 MHz
1
3.77 μs
3.69 MHz
2
2.086 μs
5.33 MHz
3
1.584 μs
When IrDA SIR mode is enabled, the UART operation is similar to when the mode is
disabled, with one exception; data transfers can only occur in half-duplex fashion when
IrDA SIR mode is enabled. This is because the IrDA SIR physical layer specifies a
minimum of 10ms delay between transmission and reception. This 10ms delay must be
generated by software.
9.8.3 CLOCK SUPPORT
The UART has two system clocks (pclk and sclk). Having the second asynchronous
serial clock (sclk) implemented accommodates accurate serial baud rate settings, as
well as APB bus interface requirements.
With the two clock design a synchronization module is implemented for synchronization
of all control and data across the two system clock boundaries.
A serial clock faster than four-times the pclk does not leave enough time for a complete
incoming character to be received and pushed into the receiver FIFO. However, in most
cases, the pclk signal is faster than the serial clock and this should never be an issue.
The serial clock modules must have time to see new register values and reset their
respective state machines. This total time is guaranteed to be no more than eight clock
cycles of the slower of the two system clocks. Therefore, no data should be transmitted
or received before this maximum time expires, after initial configuration.
9.8.4 CLOCK SUPPORT
The assertion of the UART interrupt (UART_INT) occurs whenever one of the several
prioritized interrupt types are enabled and active. The following interrupt types can be
enabled with the IER register: