Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 53
Receiver Error
Receiver Data Available
Character Timeout (in FIFO mode only)
Transmitter Holding Register Empty at/below threshold (in Programmable THRE
interrupt mode)
When an interrupt occurs, the master accesses the UART_IIR_REG to determine the
source of the interrupt before dealing with it accordingly. These interrupt types are
described in more detail in below table
Interrupt ID
Bits [3-0]
Interrupt Set and Reset Functions
Priority
Interrupt Type
Interrupt Source
Interrupt Reset Control
0001
-
None
0110
Highest
Receiver Line
status
Overrun/parity/ framing errors
or break interrupt
Reading the line status
register
0100
1
Receiver Data
Available
Receiver data available (non-
FIFO mode or FIFOs disabled)
or
RCVR FIFO trigger level reached
(FIFO mode and FIFOs enabled)
Reading the receiver buffer register (non-
FIFO mode or FIFOs disabled)
or
the FIFO drops below the trigger level
(FIFO mode and FIFOs enabled)
1100
2
Character timeout
indication
No characters in or out of the
RCVR FIFO during the last 4
character times and there is at
least 1 character in it during this
time.
Reading the receiver
buffer register
0010
3
Transmitter holding
register empty
Transmitter holding register empty
(Prog. THRE Mode disabled) or
XMIT FIFO at
or
below threshold (Prog. THRE
Mode enabled).
Reading the IIR register (if source of
interrupt);
or,
writing into THR (FIFOs or THRE Mode
not selected or disabled)
or
XMIT FIFO above threshold (FIFOs and
THRE Mode selected and enabled).
0000
4
Reserved
0111
Lowest
Reserved
-
-
9.8.5 PROGRAMMABLE THRE INTERRUPT
The UART can be configured to have a Programmable THRE Interrupt mode available
to increase system performance.
When Programmable THRE Interrupt mode is selected it can be enabled via the
Interrupt Enable Register (IER[7]). When FIFOs and the THRE Mode are implemented
and enabled, THRE Interrupts are active at, and below, a programmed transmitter FIFO
empty threshold level, as opposed to empty, as shown in the flowchart in Figure 24.