Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 55
or FIFO). The flowchart of THRE interrupt generation when not in programmable THRE
interrupt mode is shown in Figure 25.
Figure 25 Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode
9.8.6 SHADOW REGISTERS
The shadow registers shadow some of the existing register bits that are regularly
modified by software. These can be used to reduce the software overhead that is
introduced by having to perform read-modify-writes.
• UART_SRBR_REG support a host burst mode where the host increments its
address but still accesses the same Receive buffer register.
• UART_STHR support a host burst mode where the host increments its address
but still accesses the same transmit holding register.
• UART_SFE_REG accesses the FCR[0] register without accessing the other
UART_FCR_REG bits.
• UART_SRT_REG accesses the FCR[7-6] register without accessing the other
UART_FCR_REG bits.